From patchwork Mon Jun 13 16:38:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55058 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE0AD3817D23 for ; Mon, 13 Jun 2022 16:40:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE0AD3817D23 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655138457; bh=7eVd8lTYqOZV66sOXLbMKRtK+bRqq4h2Ltp5FDB+Mzo=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=SmruwC/eGABk6baxqBND+cukpROXPnH6I5rRuh4HeBqKRUjaxic8TUxGcWa6jt07j vutDkyjXTFrkIJBxGdI8dx7Nfyuni5fUEG/8I42wXz91knF+gICbIqNc2PA1Bm0g11 f7paUrrusjQ6TlNVBGhaLzGwR5QeEUMSxbQAnMNs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh601-vm12.bullet.mail.ssk.yahoo.co.jp (nh601-vm12.bullet.mail.ssk.yahoo.co.jp [182.22.90.21]) by sourceware.org (Postfix) with SMTP id B2085382B5EC for ; Mon, 13 Jun 2022 16:39:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B2085382B5EC Received: from [182.22.66.106] by nh601.bullet.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:25 -0000 Received: from [182.22.91.204] by t604.bullet.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:25 -0000 Received: from [127.0.0.1] by omp607.mail.ssk.yahoo.co.jp with NNFMP; 13 Jun 2022 16:39:25 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 105622.12755.bm@omp607.mail.ssk.yahoo.co.jp Received: (qmail 99133 invoked by alias); 13 Jun 2022 16:39:24 -0000 Received: from unknown (HELO ?192.168.2.3?) (175.177.45.189 with ) by smtp5001.mail.kks.ynwp.yahoo.co.jp with SMTP; 13 Jun 2022 16:39:24 -0000 X-YMail-JAS: Bv8L7.kVM1l_DttmnxU1LlOVR4GEeWgOai5RpESk1P3itqAM_7xpJksVCVkB6XKm2s_.rA_rX452f9R_kej7tMHXblw0g15MNFhe8Z6BwGh_r3F_B7FDY_puE1bjSC9vGQ_Ha2.DdQ-- X-Apparently-From: X-YMail-OSG: aBoJjigVM1m4YeImfpQjv3ox44t9XXdEpwPK41bPWy.9Wxu 9K4okK5_J.AL.CmPZt6DF2z2mN0nAuOoNhibTT_sZBlKw._WC1j0xloYdYbZ hOFDDI0qcY9FLOmUtfPZkwM5yfi7D54w5RFZUki.HzO87z1noueSR0g4Nz3E Yz3M9o2H8hhLgwZ1bqfxQ42WsV2JL8yu3OCggD8nacPKhkGgvJXtpqTipoZK O8eQOfLKPan.3RRAkFJ.dDr4pHxk.ePYK4QnyZW9arFGcV2DefGBTRFE4Nxg _kiGqPxgvGmJ1DvUBZBP50aGQCzH8VeLKM4IVJFhaNOk.fL0ENLFCFBuayrf glRq7gO9XqPEaznFe9PcGWZoXVgWdeocjLOTkmCvdgIP3NgwcGMRcDnjenlg RfGbh_KJOsSh7sgfV8CsQYuFtKIfpzeW_IBs6c1ir4yf_ySFDRQsUV8Tkofh QHtlhnqwreOX1dGe_n8It7HBt8FiHsn0o03QNoKBemfpiYJOGDRG.5TcwhcX oTSvo_aUJvuMMKC9f6EEPtkceqNUTmZ6aP5Y.ZZo9t5fmKit9ZSopfa0h2PW aRC6cR0F.bNgGVlSVkG8_jr9awIqnqCs2EzrqdOWmkrwNC_ChYxOr4yxpSKk 2tvMrWfGnqOWuWzFEQiDNgyu.eM.mKlq_M3oxGLLMhHE65eu1.jgIeVDgy_P DQmt9g5iO2p8C.YBqUghwLoGSihQyVQiBVOyHib2qyIKxNICVtNsiMUrM9E0 .F2pdmQSIaXO1Ij5MFeuSaZky9VCd7w0vZ5W38XUtKeHDwqIExuZZRtzXEaT HChyXoUiRUqtXNcjn6OHlMlHYNCMdrPMY1cxnPkaMN2P2IyqQvoSrQG_BmJD _TGtukLYEMkxDaVp5LK0U152j5trbarlm3g0nXP2G_htd9lBQ87jQfgbDqXB tuMkRynoz4dPti9Sd8w-- Message-ID: <84fed208-0253-b04d-c8e5-b910fc8cb321@yahoo.co.jp> Date: Tue, 14 Jun 2022 01:38:31 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH v2 1/4] xtensa: Improve shift operations more X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Changes from v1: (*shift_per_byte_omit_AND_1): changed to be split as early as possible === This patch introduces funnel shifter utilization, and rearranges existing "per-byte shift" insn patterns. gcc/ChangeLog: * config/xtensa/predicates.md (logical_shift_operator, xtensa_shift_per_byte_operator): New predicates. * config/xtensa/xtensa-protos.h (xtensa_shlrd_which_direction): New prototype. * config/xtensa/xtensa.cc (xtensa_shlrd_which_direction): New helper function for funnel shift patterns. * config/xtensa/xtensa.md (ior_op): New code iterator. (*ashlsi3_1): Replace with new split pattern. (*shift_per_byte): Unify *ashlsi3_3x, *ashrsi3_3x and *lshrsi3_3x. (*shift_per_byte_omit_AND_0, *shift_per_byte_omit_AND_1): New insn-and-split patterns that redirect to *xtensa_shift_per_byte, in order to omit unnecessary bitwise AND operation. (*shlrd_reg_, *shlrd_const_, *shlrd_per_byte_, *shlrd_per_byte__omit_AND): New insn patterns for funnel shifts. gcc/testsuite/ChangeLog: * gcc.target/xtensa/funnel_shifter.c: New. --- gcc/config/xtensa/predicates.md | 6 + gcc/config/xtensa/xtensa-protos.h | 1 + gcc/config/xtensa/xtensa.cc | 14 ++ gcc/config/xtensa/xtensa.md | 213 ++++++++++++++---- .../gcc.target/xtensa/funnel_shifter.c | 17 ++ 5 files changed, 213 insertions(+), 38 deletions(-) create mode 100644 gcc/testsuite/gcc.target/xtensa/funnel_shifter.c diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index a912e6d8bb2..bcc83ada0ae 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -164,9 +164,15 @@ (define_predicate "boolean_operator" (match_code "eq,ne")) +(define_predicate "logical_shift_operator" + (match_code "ashift,lshiftrt")) + (define_predicate "xtensa_cstoresi_operator" (match_code "eq,ne,gt,ge,lt,le")) +(define_predicate "xtensa_shift_per_byte_operator" + (match_code "ashift,ashiftrt,lshiftrt")) + (define_predicate "tls_symbol_operand" (and (match_code "symbol_ref") (match_test "SYMBOL_REF_TLS_MODEL (op) != 0"))) diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index c2fd750cd3a..2c08ed4992d 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -56,6 +56,7 @@ extern char *xtensa_emit_bit_branch (bool, bool, rtx *); extern char *xtensa_emit_movcc (bool, bool, bool, rtx *); extern char *xtensa_emit_call (int, rtx *); extern bool xtensa_tls_referenced_p (rtx); +extern enum rtx_code xtensa_shlrd_which_direction (rtx, rtx); #ifdef TREE_CODE extern void init_cumulative_args (CUMULATIVE_ARGS *, int); diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 3477e983592..df78af66714 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -2403,6 +2403,20 @@ xtensa_tls_referenced_p (rtx x) } +/* Helper function for "*shlrd_..." patterns. */ + +enum rtx_code +xtensa_shlrd_which_direction (rtx op0, rtx op1) +{ + if (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) + return ASHIFT; /* shld */ + if (GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT) + return LSHIFTRT; /* shrd */ + + return UNKNOWN; +} + + /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ static bool diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index d806d43d129..cd7ded073eb 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -83,6 +83,9 @@ ;; the same template. (define_mode_iterator HQI [HI QI]) +;; This code iterator is for *shlrd and its variants. +(define_code_iterator ior_op [ior plus]) + ;; Attributes. @@ -1267,16 +1270,6 @@ operands[1] = xtensa_copy_incoming_a7 (operands[1]); }) -(define_insn "*ashlsi3_1" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (const_int 1)))] - "TARGET_DENSITY" - "add.n\t%0, %1, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "2")]) - (define_insn "ashlsi3_internal" [(set (match_operand:SI 0 "register_operand" "=a,a") (ashift:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1289,16 +1282,14 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*ashlsi3_3x" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] - "" - "ssa8b\t%2\;sll\t%0, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "6")]) +(define_split + [(set (match_operand:SI 0 "register_operand") + (ashift:SI (match_operand:SI 1 "register_operand") + (const_int 1)))] + "TARGET_DENSITY" + [(set (match_dup 0) + (plus:SI (match_dup 1) + (match_dup 1)))]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") @@ -1312,17 +1303,6 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*ashrsi3_3x" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] - "" - "ssa8l\t%2\;sra\t%0, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "6")]) - (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1332,9 +1312,9 @@ if (which_alternative == 0) { if ((INTVAL (operands[2]) & 0x1f) < 16) - return "srli\t%0, %1, %R2"; + return "srli\t%0, %1, %R2"; else - return "extui\t%0, %1, %R2, %L2"; + return "extui\t%0, %1, %R2, %L2"; } return "ssr\t%2\;srl\t%0, %1"; } @@ -1342,13 +1322,170 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*lshrsi3_3x" +(define_insn "*shift_per_byte" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 3 "xtensa_shift_per_byte_operator" + [(match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))]))] + "!optimize_debug && optimize" +{ + switch (GET_CODE (operands[3])) + { + case ASHIFT: return "ssa8b\t%2\;sll\t%0, %1"; + case ASHIFTRT: return "ssa8l\t%2\;sra\t%0, %1"; + case LSHIFTRT: return "ssa8l\t%2\;srl\t%0, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shift_per_byte_omit_AND_0" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 4 "xtensa_shift_per_byte_operator" + [(match_operand:SI 1 "register_operand" "r") + (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3)) + (match_operand:SI 3 "const_int_operand" "i"))]))] + "!optimize_debug && optimize + && (INTVAL (operands[3]) & 0x1f) == 3 << 3" + "#" + "&& 1" + [(set (match_dup 0) + (match_op_dup 4 + [(match_dup 1) + (ashift:SI (match_dup 2) + (const_int 3))]))] + "" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shift_per_byte_omit_AND_1" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 4 "xtensa_shift_per_byte_operator" + [(match_operand:SI 1 "register_operand" "r") + (neg:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3)) + (match_operand:SI 3 "const_int_operand" "i")))]))] + "!optimize_debug && optimize + && (INTVAL (operands[3]) & 0x1f) == 3 << 3" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 5) + (neg:SI (match_dup 2))) + (set (match_dup 0) + (match_op_dup 4 + [(match_dup 1) + (ashift:SI (match_dup 5) + (const_int 3))]))] +{ + operands[5] = gen_reg_rtx (SImode); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "9")]) + +(define_insn "*shlrd_reg_" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (match_dup 2))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" +{ + switch (xtensa_shlrd_which_direction (operands[4], operands[5])) + { + case ASHIFT: return "ssl\t%2\;src\t%0, %1, %3"; + case LSHIFTRT: return "ssr\t%2\;src\t%0, %3, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn "*shlrd_const_" [(set (match_operand:SI 0 "register_operand" "=a") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] + (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "const_int_operand" "i")]) + (match_operator:SI 6 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (match_operand:SI 4 "const_int_operand" "i")])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN + && IN_RANGE (INTVAL (operands[3]), 1, 31) + && IN_RANGE (INTVAL (operands[4]), 1, 31) + && INTVAL (operands[3]) + INTVAL (operands[4]) == 32" +{ + switch (xtensa_shlrd_which_direction (operands[5], operands[6])) + { + case ASHIFT: return "ssai\t%L3\;src\t%0, %1, %2"; + case LSHIFTRT: return "ssai\t%R3\;src\t%0, %2, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn "*shlrd_per_byte_" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (ashift:SI (match_dup 2) + (const_int 3)))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" +{ + switch (xtensa_shlrd_which_direction (operands[4], operands[5])) + { + case ASHIFT: return "ssa8b\t%2\;src\t%0, %1, %3"; + case LSHIFTRT: return "ssa8l\t%2\;src\t%0, %3, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shlrd_per_byte__omit_AND" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3)) + (match_operand:SI 4 "const_int_operand" "i"))]) + (match_operator:SI 6 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (and:SI (ashift:SI (match_dup 2) + (const_int 3)) + (match_dup 4)))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN + && (INTVAL (operands[4]) & 0x1f) == 3 << 3" + "#" + "&& 1" + [(set (match_dup 0) + (ior_op:SI (match_op_dup 5 + [(match_dup 1) + (ashift:SI (match_dup 2) + (const_int 3))]) + (match_op_dup 6 + [(match_dup 3) + (neg:SI (ashift:SI (match_dup 2) + (const_int 3)))])))] "" - "ssa8l\t%2\;srl\t%0, %1" [(set_attr "type" "arith") (set_attr "mode" "SI") (set_attr "length" "6")]) diff --git a/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c b/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c new file mode 100644 index 00000000000..c8f987ccda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned int test_0(const void *addr) +{ + unsigned int n = (unsigned int)addr; + const unsigned int *a = (const unsigned int*)(n & ~3); + n = (n & 3) * 8; + return (a[0] >> n) | (a[1] << (32 - n)); +} + +unsigned int test_1(unsigned int a, unsigned int b) +{ + return (a >> 16) + (b << 16); +} + +/* { dg-final { scan-assembler-times "src" 2 } } */ From patchwork Mon Jun 13 16:28:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55057 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B8E1F3817D00 for ; Mon, 13 Jun 2022 16:39:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B8E1F3817D00 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655138398; bh=clyRiUMOXVvDNK0J+kiWFxc2+xE765WJkblu6GXASRg=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; 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(175.177.45.189 with ) by smtp5009.mail.kks.ynwp.yahoo.co.jp with SMTP; 13 Jun 2022 16:39:22 -0000 X-YMail-JAS: 0FpFOL8VM1n0Q9NSoKA.wR.TfF4yt7D3dD6pEnLG0nh.A9XqnNEvByNlXOubfsoF2qtcoZIefV3GqaBJ.OLiMghjl4R2SrQylHTMuJALJgfcvi4FD3BB44RW5jV9VuF.NPJFedpkHQ-- X-Apparently-From: X-YMail-OSG: QUyg7VoVM1lGvaESMqcBDmneHSOuJ5CJI3fIDDPEVTZ2ZV7 oJgLAYbAI75efJu3glYSYrqSoDzxyF4_qWQI_b_32HoUhjbhmGhlalksrVnj 4rLE664ORN3.Lz_Y.BuqjXChzqQA_N_QRLGxwf.W7Yh2xKhCsBmKzS_.Ivw4 f8Giykq.P6SExpcA.Ajkg8eG95ohQrUvYqnRYaDy75peUvX43bcAKM4dYApf bzQqbUy2SnAjNALsZkSBdWBQanPgRlTH18V1bJHndEE9htCuZNeZ6s0RO9ib 4PKJGsjeObpMyA9RcqqWnq0iECY9CWRqk2ohylPB.aXDmJrYL4yiwQWgUbs1 ZExHbRItbEI1R5Jqf0OgLwdm2.IHzGG0LZOzaL1OQ0ZakHoggdN4vmChAihI iexh6nhEpRZsAIAc8LnWUF6bp8uSZx1q2IPITqw_4v.JGzEA3oT3w2Vy6TBH eq0L.HaoHFXe3lXMYD0wApeo8LbkNJsDQ1iPM1EWCOMCv9.NZoI0NHtNv0SQ iXGMqm_sG1WrGqOJbFCjM.9k_boezxpw0Gd9_gu_PM3dyC_uUBq255lcNYA4 y9SW7M9KCGGd4r0g2G2bd8_y7koDYN5uOxeC.tIG5zxjz_9267As1uhFKfJv vXbGgebpWHRjlis0Xf9693LoQZW2NLmxuEnybZwVQeV.E41XX4eOd3dvgI_V TvEVpVg4GvKFnbVssVAN2eg3vSZg7ibLGHUvfM84hiEGyVh4sgp6GuhJbezs TTGqYrJ6l4iQa9yvzcOMqzCtNmI_zNE4Y8SOo17Mq4GJWUqurapO1Gsd5uUG ZdPB2fc5zJVEKeDXyY.qfUPJ0PkC6Ior_MM4Vwm6bxoo3ZhgJ5Om5JQdanNE Wd8o59eomkcOM24719JdyvjHygvIBw07tsBkUKyi8mneMX3s8y7ToMQ_kpjz gdVA19HSBI0gs_sJE2Q-- Message-ID: Date: Tue, 14 Jun 2022 01:28:43 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: [PATCH v2 4/4] xtensa: Optimize bitwise AND operation with some specific forms of constants To: Max Filippov References: Content-Language: en-US In-Reply-To: X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Cc: GCC Patches Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" On 2022/06/13 12:49, Max Filippov wrote: > Hi Suwa-san, hi! > This change produces a bunch of regression test failures in big-endian > configuration: bad news X( that point is what i was a little worried about... > E.g. for the test gcc.c-torture/execute/struct-ini-2.c > the following assembly code is generated now: > and the following code was generated before this change: - .literal .LC1, -4096 - l32r a10, .LC1 - and a10, a8, a10 + extui a10, a8, 16, 4 // wrong! must be 12, 4 + slli a10, a10, 12 and of course, '(zero_extract)' is endianness-sensitive. (ref. 14.11 Bit-Fields, gcc-internals) the all patches that i previouly posted do not match or emit '(zero_extract)', except for this case. === This patch offers several insn-and-split patterns for bitwise AND with register and constant that can be represented as: i. 1's least significant N bits and the others 0's (17 <= N <= 31) ii. 1's most significant N bits and the others 0's (12 <= N <= 31) iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a "MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30) And also offers shortcuts for conditional branch if each of the abovementioned operations is (not) equal to zero. gcc/ChangeLog: * config/xtensa/predicates.md (shifted_mask_operand): New predicate. * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): New insn-and-split pattern. (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, *masktrue_const_shifted_mask): Ditto. --- gcc/config/xtensa/predicates.md | 10 ++ gcc/config/xtensa/xtensa.md | 179 ++++++++++++++++++++++++++++++++ 2 files changed, 189 insertions(+) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index bcc83ada0ae..d63a6cf034c 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -52,6 +52,16 @@ (match_test "xtensa_mask_immediate (INTVAL (op))")) (match_operand 0 "register_operand"))) +(define_predicate "shifted_mask_operand" + (match_code "const_int") +{ + HOST_WIDE_INT mask = INTVAL (op); + int shift = ctz_hwi (mask); + + return IN_RANGE (shift, 1, 31) + && xtensa_mask_immediate ((uint32_t)mask >> shift); +}) + (define_predicate "extui_fldsz_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index a4477e2207e..5d0f346b01a 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -645,6 +645,83 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) +(define_insn_and_split "*andsi3_const_pow2_minus_one" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (lshiftrt:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*andsi3_const_negative_pow2" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*andsi3_const_shifted_mask" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")))] + "! xtensa_simm12b (INTVAL (operands[2]))" + "#" + "&& 1" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 3) + (match_dup 4))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1); + int mask_pos = shift; + if (BITS_BIG_ENDIAN) + mask_pos = (32 - (mask_size + shift)) & 0x1f; + operands[2] = GEN_INT (shift); + operands[3] = GEN_INT (mask_size); + operands[4] = GEN_INT (mask_pos); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && ctz_hwi (INTVAL (operands[2])) == 1") + (const_int 5) + (const_int 6)))]) + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=a") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -1649,6 +1726,108 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_insn_and_split "*masktrue_const_pow2_minus_one" + [(set (pc) + (if_then_else (match_operator 3 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "IN_RANGE (exact_log2 (INTVAL (operands[1]) + 1), 17, 31)" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 4) + (ashift:SI (match_dup 0) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 3 + [(match_dup 4) + (const_int 0)]) + (label_ref (match_dup 2)) + (pc)))] +{ + operands[1] = GEN_INT (32 - floor_log2 (INTVAL (operands[1]) + 1)); + operands[4] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[1]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*masktrue_const_negative_pow2" + [(set (pc) + (if_then_else (match_operator 3 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "IN_RANGE (exact_log2 (-INTVAL (operands[1])), 12, 30)" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 4) + (lshiftrt:SI (match_dup 0) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 3 + [(match_dup 4) + (const_int 0)]) + (label_ref (match_dup 2)) + (pc)))] +{ + operands[1] = GEN_INT (floor_log2 (-INTVAL (operands[1]))); + operands[4] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + +(define_insn_and_split "*masktrue_const_shifted_mask" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "shifted_mask_operand" "i")) + (match_operand:SI 2 "const_int_operand" "i")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "(INTVAL (operands[2]) & ((1 << ctz_hwi (INTVAL (operands[1]))) - 1)) == 0 + && xtensa_b4const_or_zero ((uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])))" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 6) + (zero_extract:SI (match_dup 0) + (match_dup 5) + (match_dup 1))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 6) + (match_dup 2)]) + (label_ref (match_dup 3)) + (pc)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[1]); + int shift = ctz_hwi (mask); + int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1); + int mask_pos = shift; + if (BITS_BIG_ENDIAN) + mask_pos = (32 - (mask_size + shift)) & 0x1f; + operands[1] = GEN_INT (mask_pos); + operands[2] = GEN_INT ((uint32_t)INTVAL (operands[2]) >> shift); + operands[5] = GEN_INT (mask_size); + operands[6] = gen_reg_rtx (SImode); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && (uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])) == 0") + (const_int 5) + (const_int 6)))]) + ;; Zero-overhead looping support.