From patchwork Mon Jun 13 15:15:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 55056 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7911B3851A96 for ; Mon, 13 Jun 2022 15:16:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7911B3851A96 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655133375; bh=IPR98qQySHX0/A6Vel1CsZMQ7249ad1CpBrz8+IGbwI=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=upHNUCIIa5XK5Ou1rH8mUb4GafWDS8AX37aCS0zHuR2J+/wSAL8GfjLB1DaFlomrK eruDBpMPlV8AuCgyGr2hB8JysBHr9vVWM2tcOK/vSZQDybVzvHPTlweuhcZoeGcchd mBs/5hxbzveRaR3lMhaGMSdH6jPYqi+nGTbs4OYQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by sourceware.org (Postfix) with ESMTPS id 796AA3852760 for ; Mon, 13 Jun 2022 15:15:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 796AA3852760 Received: by mail-qv1-xf2e.google.com with SMTP id j2so4512529qvp.9 for ; Mon, 13 Jun 2022 08:15:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=IPR98qQySHX0/A6Vel1CsZMQ7249ad1CpBrz8+IGbwI=; b=G/xa5ZbYnUvwU3uKYDHwSS52HlH54ehMo7Ptf0qiAteHoCshl6Gp3w8XLM9GFcKNVE ALf+NR8dqAFrSBbY5MEQAQIWSwTxwol9D2WAK6kW75mxKYVPx6IIKOAIKGGRniUNH1y7 iu32KpbHL2nHgSJ0lD7QsBfAxCeB39MNao7JmP7WmAgil2f0i/SUqeDAWzQ5PG/16sAw nwP5Iz2V3IVmaTQW+ZnqWATZAQxNtjo8YJikLKxMFMoEytVFYzy4MlRvDzP9OYzeRQi2 UtePsL5F4C34hTdlOdz+IyNkNc83N0iu3kkHHkTrtbrLxQ8I5fjjeguSQSfktqUHYZUe 2Bnw== X-Gm-Message-State: AJIora8PXeuQMJ49d81IbAnnUDBq4xWcmzImV2QEelCONcM3sbmufRIJ ZmTwIdjb/i6JdMBXaDaWWME6/x5nl2wVGrWm+Mc2t2du3IU= X-Google-Smtp-Source: AGRyM1s6DWzQdJu6hfY8UK1w0PGRpaz3veHd3SD7Om/mmqB2p+rpchUS1E8BtnfBp7Z8zlC7IRe89u3UpE86eB5RLws= X-Received: by 2002:a05:6214:268b:b0:46b:91d2:f2e5 with SMTP id gm11-20020a056214268b00b0046b91d2f2e5mr219941qvb.125.1655133344535; Mon, 13 Jun 2022 08:15:44 -0700 (PDT) MIME-Version: 1.0 Date: Mon, 13 Jun 2022 17:15:33 +0200 Message-ID: Subject: [PATCH] i386: Return true for (SUBREG (MEM....)) in register_no_elim_operand [PR105927] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Under certain conditions register_operand predicate also allows subregs of memory operands. When RTL checking is enabled, these will fail with REGNO (op). Allow subregs of memory operands, these are guaranteed to be reloaded to a register. 2022-06-13 Uroš Bizjak gcc/ChangeLog: PR target/105927 * config/i386/predicates.md (register_no_elim_operand): Return true for subreg of a memory operand. gcc/testsuite/ChangeLog: PR target/105927 * gcc.target/i386/pr105927.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 848a79a8d16..128144f1050 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -672,6 +672,12 @@ (define_predicate "register_no_elim_operand" { if (SUBREG_P (op)) op = SUBREG_REG (op); + + /* Before reload, we can allow (SUBREG (MEM...)) as a register operand + because it is guaranteed to be reloaded into one. */ + if (MEM_P (op)) + return true; + return !(op == arg_pointer_rtx || op == frame_pointer_rtx || IN_RANGE (REGNO (op), @@ -685,6 +691,7 @@ (define_predicate "index_register_operand" { if (SUBREG_P (op)) op = SUBREG_REG (op); + if (reload_completed) return REG_OK_FOR_INDEX_STRICT_P (op); else diff --git a/gcc/testsuite/gcc.target/i386/pr105927.c b/gcc/testsuite/gcc.target/i386/pr105927.c new file mode 100644 index 00000000000..602461806fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105927.c @@ -0,0 +1,18 @@ +/* PR target/105927 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O1 -fno-tree-dce -mtune=k6-3 -msse2" } */ + +typedef _Float16 __attribute__((__vector_size__(4))) U; +typedef _Float16 __attribute__((__vector_size__(2))) V; +typedef short __attribute__((__vector_size__(4))) W; +V v; +U u; + +extern void bar(W i); + +void +foo(void) +{ + U x = __builtin_shufflevector(v, u, 2, 0); + bar(x >= 0); +}