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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v7-20020a1709062f0700b006fea2705d18sm3805416eji.210.2022.06.13.06.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 06:20:45 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro Date: Mon, 13 Jun 2022 15:20:41 +0200 Message-Id: <20220613132042.2972081-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The current description of RISCV_CORE() does not match the implementation. This commit provides a fix for that. gcc/ChangeLog: * config/riscv/riscv-cores.def: Fix comment. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index ecb5e213d98..60bcadbb034 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -21,15 +21,13 @@ Before using #include to read this file, define a macro: - RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO) + RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO) The CORE_NAME is the name of the core, represented as a string. - The ARCH is the default arch of the core, represented as a string, - can be NULL if no default arch. - The MICRO_ARCH is the name of the core for which scheduling decisions - will be made, represented as an identifier. - The TUNE_INFO is the detail cost model for this core, represented as an - identifier, reference to riscv-tunes.def. */ + The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i" + or "rv64gc_zifencei"). + The TUNE_INFO is a string that references the detail tuning information + for this core (refer to riscv_tune_info_table for possible values). */ RISCV_CORE("sifive-e20", "rv32imc", "rocket") RISCV_CORE("sifive-e21", "rv32imac", "rocket") From patchwork Mon Jun 13 13:20:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 55047 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 97B1F3852744 for ; Mon, 13 Jun 2022 13:21:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 39DA73852745 for ; Mon, 13 Jun 2022 13:20:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 39DA73852745 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x635.google.com with SMTP id n10so11148296ejk.5 for ; Mon, 13 Jun 2022 06:20:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lenfI+aC34Y/oHg4qapxq0OoJsy4Y7fJHfshXPSjmng=; b=Kkb6t3DXaU5eppGWisut6MURzmljR1tfSei7vPK0vqVDAaslgNxe+c3oF3SVRANKxS rAlQgNw9TJYJqHGPgRE84W+/C/224HC2d1IVLsB4gbUrfq4D44EmlrAw2bOjH+qdTRDy 0EJEFsFT9XPoZCqn5DkYRIisGKwwv5C9V0KMSZQaIqwih4z5dEFmTDjUm5GiN0oeU6Ro AqrSl868bIXCa8W37LbfiAXiN+TYayxu//2IGck5ozbAskJTobzVI/p4I06amn80C394 5OSLcAGApTeimZ8jTryUrZxKF9CgI1wP1FCF1eyXpnpQrMZDiyh8j3J3QqdK12r4ybkB lIUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lenfI+aC34Y/oHg4qapxq0OoJsy4Y7fJHfshXPSjmng=; b=kJMoHXqAdq4iuXm3Vnu3kt1NyK3zFqCnqfxAXG88m2UREe3gU0Tpw6dL4GsPER62vR dggRf2W51l/v0OoV+6G5aMV1Fdh+Fy4wa08aNCD413OwXB3cLUotGk8R61ZUm06Wgbn6 +afna1ov3qwy74WV9qq77i2f2fqic03Q5JF1FO6o1X3fMzkhmvq6J7nEHiERN/QeTOui GAXBcEgmgVTH05OVXzilOL6O5HrnJ2zHrCqNCBTOBOQFwLfY3Ok0e1OuqgbJNKcCIaXS lldaWtZsrPowHgbIJUragfvoR/kKHQriXb8q7mknRvEbRMd56eUFxnV1unQC6+Ffnr0X rAZg== X-Gm-Message-State: AOAM530mu56o6Eppc9N/nkqX2+PrqQ/7mjEeTONsgfB9zdQPIm8o0AWk j3oI7OBtAlxrxy0sECtiyn3ve+IkMUALmg== X-Google-Smtp-Source: ABdhPJylE5E5U9Ndfp3emUJexhQwLDjBoAZWt16BsAkfP4QHL19Pd8tUxjQdKYc2YFawekT4ao8t5Q== X-Received: by 2002:a17:907:8a03:b0:711:f3c3:71a6 with SMTP id sc3-20020a1709078a0300b00711f3c371a6mr25562333ejc.659.1655126446820; Mon, 13 Jun 2022 06:20:46 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v7-20020a1709062f0700b006fea2705d18sm3805416eji.210.2022.06.13.06.20.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 06:20:46 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core Date: Mon, 13 Jun 2022 15:20:42 +0200 Message-Id: <20220613132042.2972081-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220613132042.2972081-1-christoph.muellner@vrull.eu> References: <20220613132042.2972081-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This adds Allwinner's D1 to the list of known cores. The Allwinner includes a single-core XuanTie C906 and is available for quite some time. Note, that the tuning struct for the C906 is already part of GCC. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1". Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 60bcadbb034..dd97ece376f 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") + #undef RISCV_CORE