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(175.177.45.176 with ) by smtp6009.mail.ssk.ynwp.yahoo.co.jp with SMTP; 12 Jun 2022 06:43:14 -0000 X-YMail-JAS: zyg_6jwVM1lfvjen6.T1L6wq3aBCfMEEjCLXYnMgll2x1.ToQ8Ya.N3QgbDZyEsCit0KJ2OoDcJSdHVKv80eE8l4niLdzwIYq8mt4a6e6Q9TZPGmLfB8Awh.DOMSPwu7JmOak5Irtw-- X-Apparently-From: X-YMail-OSG: NecWElcVM1lhp8xIYvdduDvQNBb8C4FuLTjce1SNHqKKoYb syDmAivSkljvbODFs6rRWRKJ3_7ZDk.L6G4gN6XtNC5.xL20Aflk2pvTUbia uXpJoXg.vRYma1mIF69ju_.TLakiAGDliP7IgcnsnmllOOUS0uRLbGtlncrg AOxDmOCByywqJbOevIGvHhUT1rmFKKDxc1N1H3bzytwI1T77YlRyrApJ.vPU v4LJ_0IX5I1KbODfBmtF3FLinWbSv7rCCGDCKtZ9G.pb40EUBh1Erb_pOq.J WuRhgjAwE_yPorSU.V6HcCag5XZJdhvdsZ60wekklvVr1C7mwVNa8mHxyCty bXvLcZcu6fCgi_B1UKAtjpZkdxm.4.siJe8IfL3hNWI3yhpFgTGXLsJMgmlL icq6EQE2ed29vheEMP2wBgV3_mmg1tN_7pFO7sY7OcAJVj5lL6_aTy7CmP.b vq4m.UX8gUrs_2y4ZCxAAsz.GsUdOuJazWJAQvYW1m7QfvMTCfobhW8ldBWd C6PWw3wfwxe2DDBS4PQJFoGYl8aRGapsqUrHHtwWfKhBYkAbcEGPO_anzRYf YLwycmb4bpEw_tJy4o1oUwZRyrEr.m.DuN5QSKVxgsiskI_KsKblHat6xh3G 87Xpwa1.RfcSRp1bcfcc5Bu8i6oMq6QcZ2wWnozRiKcX4E78N6tLwVdhgPhi Ijl8d1vPakGR4ag4O.A7B677Mr4jjMi97J_pVDdcGLRPtL1OcXm7QhZk.457 kkF3vTXsSuS1_Y1nXk6ryaz00VxGLE4HA7jWG9lB1C3gDmLUPpbElfNrhr9w ibbF2zQle4yGDvN96FzyVMFtQRNGlBFGb8n.kEcgwRlxcvqCE2eHJa1jiqu. g83nKgFeQiqhM4UFmiMOlna0Cv0iCCXvhBEstsT0ET9CGSwSy6YLU9VYMEi0 pXEJwiZ8jVKnLxKUkGw-- Message-ID: <196a3880-b4ee-6c6c-bdc1-b99800c43705@yahoo.co.jp> Date: Sun, 12 Jun 2022 15:31:24 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH 1/4] xtensa: Improve shift operations more X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch introduces funnel shifter utilization, and rearranges existing "per-byte shift" insn patterns. gcc/ChangeLog: * config/xtensa/predicates.md (logical_shift_operator, xtensa_shift_per_byte_operator): New predicates. * config/xtensa/xtensa-protos.h (xtensa_shlrd_which_direction): New prototype. * config/xtensa/xtensa.cc (xtensa_shlrd_which_direction): New helper function for funnel shift patterns. * config/xtensa/xtensa.md (ior_op): New code iterator. (*ashlsi3_1): Replace with new split pattern. (*shift_per_byte): Unify *ashlsi3_3x, *ashrsi3_3x and *lshrsi3_3x. (*shift_per_byte_omit_AND_0, *shift_per_byte_omit_AND_1): New insn-and-split patterns that redirect to *xtensa_shift_per_byte, in order to omit unnecessary bitwise AND operation. (*shlrd_reg_, *shlrd_const_, *shlrd_per_byte_, *shlrd_per_byte__omit_AND): New insn patterns for funnel shifts. gcc/testsuite/ChangeLog: * gcc.target/xtensa/funnel_shifter.c: New. --- gcc/config/xtensa/predicates.md | 6 + gcc/config/xtensa/xtensa-protos.h | 1 + gcc/config/xtensa/xtensa.cc | 14 ++ gcc/config/xtensa/xtensa.md | 212 ++++++++++++++---- .../gcc.target/xtensa/funnel_shifter.c | 17 ++ 5 files changed, 212 insertions(+), 38 deletions(-) create mode 100644 gcc/testsuite/gcc.target/xtensa/funnel_shifter.c diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index a912e6d8bb2..bcc83ada0ae 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -164,9 +164,15 @@ (define_predicate "boolean_operator" (match_code "eq,ne")) +(define_predicate "logical_shift_operator" + (match_code "ashift,lshiftrt")) + (define_predicate "xtensa_cstoresi_operator" (match_code "eq,ne,gt,ge,lt,le")) +(define_predicate "xtensa_shift_per_byte_operator" + (match_code "ashift,ashiftrt,lshiftrt")) + (define_predicate "tls_symbol_operand" (and (match_code "symbol_ref") (match_test "SYMBOL_REF_TLS_MODEL (op) != 0"))) diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index c2fd750cd3a..2c08ed4992d 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -56,6 +56,7 @@ extern char *xtensa_emit_bit_branch (bool, bool, rtx *); extern char *xtensa_emit_movcc (bool, bool, bool, rtx *); extern char *xtensa_emit_call (int, rtx *); extern bool xtensa_tls_referenced_p (rtx); +extern enum rtx_code xtensa_shlrd_which_direction (rtx, rtx); #ifdef TREE_CODE extern void init_cumulative_args (CUMULATIVE_ARGS *, int); diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 3477e983592..df78af66714 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -2403,6 +2403,20 @@ xtensa_tls_referenced_p (rtx x) } +/* Helper function for "*shlrd_..." patterns. */ + +enum rtx_code +xtensa_shlrd_which_direction (rtx op0, rtx op1) +{ + if (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) + return ASHIFT; /* shld */ + if (GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT) + return LSHIFTRT; /* shrd */ + + return UNKNOWN; +} + + /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ static bool diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index d806d43d129..bf79099f21b 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -83,6 +83,9 @@ ;; the same template. (define_mode_iterator HQI [HI QI]) +;; This code iterator is for *shlrd and its variants. +(define_code_iterator ior_op [ior plus]) + ;; Attributes. @@ -1267,16 +1270,6 @@ operands[1] = xtensa_copy_incoming_a7 (operands[1]); }) -(define_insn "*ashlsi3_1" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (const_int 1)))] - "TARGET_DENSITY" - "add.n\t%0, %1, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "2")]) - (define_insn "ashlsi3_internal" [(set (match_operand:SI 0 "register_operand" "=a,a") (ashift:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1289,16 +1282,14 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*ashlsi3_3x" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] - "" - "ssa8b\t%2\;sll\t%0, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "6")]) +(define_split + [(set (match_operand:SI 0 "register_operand") + (ashift:SI (match_operand:SI 1 "register_operand") + (const_int 1)))] + "TARGET_DENSITY" + [(set (match_dup 0) + (plus:SI (match_dup 1) + (match_dup 1)))]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") @@ -1312,17 +1303,6 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*ashrsi3_3x" - [(set (match_operand:SI 0 "register_operand" "=a") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] - "" - "ssa8l\t%2\;sra\t%0, %1" - [(set_attr "type" "arith") - (set_attr "mode" "SI") - (set_attr "length" "6")]) - (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=a,a") (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1332,9 +1312,9 @@ if (which_alternative == 0) { if ((INTVAL (operands[2]) & 0x1f) < 16) - return "srli\t%0, %1, %R2"; + return "srli\t%0, %1, %R2"; else - return "extui\t%0, %1, %R2, %L2"; + return "extui\t%0, %1, %R2, %L2"; } return "ssr\t%2\;srl\t%0, %1"; } @@ -1342,13 +1322,169 @@ (set_attr "mode" "SI") (set_attr "length" "3,6")]) -(define_insn "*lshrsi3_3x" +(define_insn "*shift_per_byte" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 3 "xtensa_shift_per_byte_operator" + [(match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))]))] + "!optimize_debug && optimize" +{ + switch (GET_CODE (operands[3])) + { + case ASHIFT: return "ssa8b\t%2\;sll\t%0, %1"; + case ASHIFTRT: return "ssa8l\t%2\;sra\t%0, %1"; + case LSHIFTRT: return "ssa8l\t%2\;srl\t%0, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shift_per_byte_omit_AND_0" [(set (match_operand:SI 0 "register_operand" "=a") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") - (ashift:SI (match_operand:SI 2 "register_operand" "r") - (const_int 3))))] + (match_operator:SI 4 "xtensa_shift_per_byte_operator" + [(match_operand:SI 1 "register_operand" "r") + (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3)) + (match_operand:SI 3 "const_int_operand" "i"))]))] + "!optimize_debug && optimize + && (INTVAL (operands[3]) & 0x1f) == 3 << 3" + "#" + "&& 1" + [(set (match_dup 0) + (match_op_dup 4 + [(match_dup 1) + (ashift:SI (match_dup 2) + (const_int 3))]))] + "" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shift_per_byte_omit_AND_1" + [(set (match_operand:SI 0 "register_operand" "=a") + (match_operator:SI 5 "xtensa_shift_per_byte_operator" + [(match_operand:SI 2 "register_operand" "r") + (neg:SI (and:SI (ashift:SI (match_operand:SI 3 "register_operand" "r") + (const_int 3)) + (match_operand:SI 4 "const_int_operand" "i")))])) + (clobber (match_scratch:SI 1 "=&a"))] + "!optimize_debug && optimize + && (INTVAL (operands[4]) & 0x1f) == 3 << 3" + "#" + "&& reload_completed" + [(set (match_dup 1) + (neg:SI (match_dup 3))) + (set (match_dup 0) + (match_op_dup 5 + [(match_dup 2) + (ashift:SI (match_dup 1) + (const_int 3))]))] + "" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "9")]) + +(define_insn "*shlrd_reg_" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (match_dup 2))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" +{ + switch (xtensa_shlrd_which_direction (operands[4], operands[5])) + { + case ASHIFT: return "ssl\t%2\;src\t%0, %1, %3"; + case LSHIFTRT: return "ssr\t%2\;src\t%0, %3, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn "*shlrd_const_" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 3 "const_int_operand" "i")]) + (match_operator:SI 6 "logical_shift_operator" + [(match_operand:SI 2 "register_operand" "r") + (match_operand:SI 4 "const_int_operand" "i")])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN + && IN_RANGE (INTVAL (operands[3]), 1, 31) + && IN_RANGE (INTVAL (operands[4]), 1, 31) + && INTVAL (operands[3]) + INTVAL (operands[4]) == 32" +{ + switch (xtensa_shlrd_which_direction (operands[5], operands[6])) + { + case ASHIFT: return "ssai\t%L3\;src\t%0, %1, %2"; + case LSHIFTRT: return "ssai\t%R3\;src\t%0, %2, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn "*shlrd_per_byte_" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 4 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3))]) + (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (ashift:SI (match_dup 2) + (const_int 3)))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[4], operands[5]) != UNKNOWN" +{ + switch (xtensa_shlrd_which_direction (operands[4], operands[5])) + { + case ASHIFT: return "ssa8b\t%2\;src\t%0, %1, %3"; + case LSHIFTRT: return "ssa8l\t%2\;src\t%0, %3, %1"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*shlrd_per_byte__omit_AND" + [(set (match_operand:SI 0 "register_operand" "=a") + (ior_op:SI (match_operator:SI 5 "logical_shift_operator" + [(match_operand:SI 1 "register_operand" "r") + (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") + (const_int 3)) + (match_operand:SI 4 "const_int_operand" "i"))]) + (match_operator:SI 6 "logical_shift_operator" + [(match_operand:SI 3 "register_operand" "r") + (neg:SI (and:SI (ashift:SI (match_dup 2) + (const_int 3)) + (match_dup 4)))])))] + "!optimize_debug && optimize + && xtensa_shlrd_which_direction (operands[5], operands[6]) != UNKNOWN + && (INTVAL (operands[4]) & 0x1f) == 3 << 3" + "#" + "&& 1" + [(set (match_dup 0) + (ior_op:SI (match_op_dup 5 + [(match_dup 1) + (ashift:SI (match_dup 2) + (const_int 3))]) + (match_op_dup 6 + [(match_dup 3) + (neg:SI (ashift:SI (match_dup 2) + (const_int 3)))])))] "" - "ssa8l\t%2\;srl\t%0, %1" [(set_attr "type" "arith") (set_attr "mode" "SI") (set_attr "length" "6")]) diff --git a/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c b/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c new file mode 100644 index 00000000000..c8f987ccda9 --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/funnel_shifter.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned int test_0(const void *addr) +{ + unsigned int n = (unsigned int)addr; + const unsigned int *a = (const unsigned int*)(n & ~3); + n = (n & 3) * 8; + return (a[0] >> n) | (a[1] << (32 - n)); +} + +unsigned int test_1(unsigned int a, unsigned int b) +{ + return (a >> 16) + (b << 16); +} + +/* { dg-final { scan-assembler-times "src" 2 } } */ From patchwork Sun Jun 12 06:33:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55037 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2C528386F471 for ; Sun, 12 Jun 2022 06:44:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2C528386F471 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655016287; bh=xueCJrU0SHeiF63xTDleFvTFqaBnDvD9eDaJ0KsFeRw=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; 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(175.177.45.176 with ) by smtp6005.mail.ssk.ynwp.yahoo.co.jp with SMTP; 12 Jun 2022 06:43:16 -0000 X-YMail-JAS: 3Lz86mwVM1lEjtba.4keyz1lTye2CUGR15qpXnD8H_23c0iO4n_ls1fTTuXBLkLPcKNFxERaV4f5Q3VrPTn7TBiRjZc_3_VbHgI66jQhCnWJMRy1Jb7NIZzAt4YcS7ZinzbquGosSg-- X-Apparently-From: X-YMail-OSG: ORjJ49AVM1mc4jvKjWdeeqzTTu84y4f0UWIKXwdxKX.9qVU DB0VCGzlihFRzVijtgJkFOe.YUzqiqUjAB2xfR8DPMiqa4l37UHAutmmYMYC NH0lXiIzIr.gOnRM2iykdWZOCD9giTaMO2W9OThwgU76N1RRJHTSp0nUkwBg 4wHdw7jpHGq9aDfILEeDg0JabgcRZ.oZCDAH6GxyB5dN5MH7HOz1RwIpVS6y 3dLoZ7gBHNpR4zdQhkOMLoVDVhMtQFKkhbkRH2YNhg3lNFTGKC_UHmpVqQSl Zh337TWEaXxMU_O8RVfWpQ86bWAPJVTew8eVaZxu1gMFVZw94gJxQ.h7i7vS o46gtIzTD.LDbON63xwzCwwBeTRWJ5S0QJC.NBph.uOsSSD.8bONrbnX2G0y mYO_QVzOIcGaZNNJDrcDs9mGDW7sZcf7TbJSNm0sJVcuaquZdtq_Zt4nsrj1 uSNidvJ7Dyyb20zx6Qr5ZJEURr9bnAc04.9Nw3Vac7o8_GLO7T0g7uYs0NiQ fXp9kiTaADVDp2v2Mh1pUYXWvgkIxwCpmvN3mnHsBifTO_a2GK0IAG.Zoppg .RgH6WU5YlyCcAo1dkZAKumJ7VzKUA64OwyOctdmE_k7ecd1wVzbED6tTP8d W3.ftBT3hoNJ2TGkRVxmp8PD5cqcT2BGw5owyVub_0zd3U724yZdKKv_lDKY y3BvUM_5n8gWtuvd7VGPsh5v8FJBAUm9qEgrNFCMwmjpLwjSaLZOWN17i2vs hkE4HvvT5fBF57gBMUFKS13cSEiSctMWbhDcSAtlp6IkGTyvHmAmcVAgHiPu 9Cxely3nDIFDJBlDJXpZvptQWZocqcc3YSz7hecGeKZ.WpPltgexMDGazbmf QIKo3.JopGXDW6gcKtGE12xuHIvJOHiOqXUOeHgqfvDcps8aliKK10g_9bPz vXEjssa0bvKpAXeTa2lE- Message-ID: Date: Sun, 12 Jun 2022 15:33:00 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH 2/4] xtensa: Simplify conditional branch/move insn patterns X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" No need to describe the "false side" conditional insn patterns anymore. gcc/ChangeLog: * config/xtensa/xtensa-protos.h (xtensa_emit_branch): Remove the first argument. (xtensa_emit_bit_branch): Remove it because now called only from the output statement of *bittrue insn pattern. * config/xtensa/xtensa.cc (gen_int_relational): Remove the last argument 'p_invert', and make so that the condition is reversed by itself as needed. (xtensa_expand_conditional_branch): Share the common path, and remove condition inversion code. (xtensa_emit_branch, xtensa_emit_movcc): Simplify by removing the "false side" pattern. (xtensa_emit_bit_branch): Remove it because of the abovementioned reason, and move the function body to *bittrue insn pattern. * config/xtensa/xtensa.md (*bittrue): Transplant the output statement from removed xtensa_emit_bit_branch(). (*bfalse, *ubfalse, *bitfalse, *maskfalse): Remove the "false side" insn patterns. --- gcc/config/xtensa/xtensa-protos.h | 3 +- gcc/config/xtensa/xtensa.cc | 111 ++++++++++------------------ gcc/config/xtensa/xtensa.md | 117 ++++++++---------------------- 3 files changed, 70 insertions(+), 161 deletions(-) diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index 2c08ed4992d..168ad70710b 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -51,8 +51,7 @@ extern void xtensa_expand_nonlocal_goto (rtx *); extern void xtensa_expand_compare_and_swap (rtx, rtx, rtx, rtx); extern void xtensa_expand_atomic (enum rtx_code, rtx, rtx, rtx, bool); extern void xtensa_emit_loop_end (rtx_insn *, rtx *); -extern char *xtensa_emit_branch (bool, bool, rtx *); -extern char *xtensa_emit_bit_branch (bool, bool, rtx *); +extern char *xtensa_emit_branch (bool, rtx *); extern char *xtensa_emit_movcc (bool, bool, bool, rtx *); extern char *xtensa_emit_call (int, rtx *); extern bool xtensa_tls_referenced_p (rtx); diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index df78af66714..58b6eb0b711 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -118,7 +118,7 @@ const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] = static void xtensa_option_override (void); static enum internal_test map_test_to_internal_test (enum rtx_code); -static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *); +static rtx gen_int_relational (enum rtx_code, rtx, rtx); static rtx gen_float_relational (enum rtx_code, rtx, rtx); static rtx gen_conditional_move (enum rtx_code, machine_mode, rtx, rtx); static rtx fixup_subreg_mem (rtx); @@ -680,8 +680,7 @@ map_test_to_internal_test (enum rtx_code test_code) static rtx gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ rtx cmp0, /* first operand to compare */ - rtx cmp1, /* second operand to compare */ - int *p_invert /* whether branch needs to reverse test */) + rtx cmp1 /* second operand to compare */) { struct cmp_info { @@ -713,6 +712,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ enum internal_test test; machine_mode mode; struct cmp_info *p_info; + int invert; test = map_test_to_internal_test (test_code); gcc_assert (test != ITEST_MAX); @@ -749,9 +749,9 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ } /* See if we need to invert the result. */ - *p_invert = ((GET_CODE (cmp1) == CONST_INT) - ? p_info->invert_const - : p_info->invert_reg); + invert = ((GET_CODE (cmp1) == CONST_INT) + ? p_info->invert_const + : p_info->invert_reg); /* Comparison to constants, may involve adding 1 to change a LT into LE. Comparison between two registers, may involve switching operands. */ @@ -768,7 +768,9 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ cmp1 = temp; } - return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1); + return gen_rtx_fmt_ee (invert ? reverse_condition (p_info->test_code) + : p_info->test_code, + VOIDmode, cmp0, cmp1); } @@ -827,45 +829,33 @@ xtensa_expand_conditional_branch (rtx *operands, machine_mode mode) enum rtx_code test_code = GET_CODE (operands[0]); rtx cmp0 = operands[1]; rtx cmp1 = operands[2]; - rtx cmp; - int invert; - rtx label1, label2; + rtx cmp, label; switch (mode) { + case E_SFmode: + if (TARGET_HARD_FLOAT) + { + cmp = gen_float_relational (test_code, cmp0, cmp1); + break; + } + /* FALLTHRU */ + case E_DFmode: default: fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); case E_SImode: - invert = FALSE; - cmp = gen_int_relational (test_code, cmp0, cmp1, &invert); - break; - - case E_SFmode: - if (!TARGET_HARD_FLOAT) - fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, - cmp0, cmp1)); - invert = FALSE; - cmp = gen_float_relational (test_code, cmp0, cmp1); + cmp = gen_int_relational (test_code, cmp0, cmp1); break; } /* Generate the branch. */ - - label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]); - label2 = pc_rtx; - - if (invert) - { - label2 = label1; - label1 = pc_rtx; - } - + label = gen_rtx_LABEL_REF (VOIDmode, operands[3]); emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, - label1, - label2))); + label, + pc_rtx))); } @@ -2068,21 +2058,20 @@ xtensa_emit_loop_end (rtx_insn *insn, rtx *operands) char * -xtensa_emit_branch (bool inverted, bool immed, rtx *operands) +xtensa_emit_branch (bool immed, rtx *operands) { static char result[64]; - enum rtx_code code; + enum rtx_code code = GET_CODE (operands[3]); const char *op; - code = GET_CODE (operands[3]); switch (code) { - case EQ: op = inverted ? "ne" : "eq"; break; - case NE: op = inverted ? "eq" : "ne"; break; - case LT: op = inverted ? "ge" : "lt"; break; - case GE: op = inverted ? "lt" : "ge"; break; - case LTU: op = inverted ? "geu" : "ltu"; break; - case GEU: op = inverted ? "ltu" : "geu"; break; + case EQ: op = "eq"; break; + case NE: op = "ne"; break; + case LT: op = "lt"; break; + case GE: op = "ge"; break; + case LTU: op = "ltu"; break; + case GEU: op = "geu"; break; default: gcc_unreachable (); } @@ -2101,32 +2090,6 @@ xtensa_emit_branch (bool inverted, bool immed, rtx *operands) } -char * -xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands) -{ - static char result[64]; - const char *op; - - switch (GET_CODE (operands[3])) - { - case EQ: op = inverted ? "bs" : "bc"; break; - case NE: op = inverted ? "bc" : "bs"; break; - default: gcc_unreachable (); - } - - if (immed) - { - unsigned bitnum = INTVAL (operands[1]) & 0x1f; - operands[1] = GEN_INT (bitnum); - sprintf (result, "b%si\t%%0, %%d1, %%2", op); - } - else - sprintf (result, "b%s\t%%0, %%1, %%2", op); - - return result; -} - - char * xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) { @@ -2135,12 +2098,14 @@ xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) const char *op; code = GET_CODE (operands[4]); + if (inverted) + code = reverse_condition (code); if (isbool) { switch (code) { - case EQ: op = inverted ? "t" : "f"; break; - case NE: op = inverted ? "f" : "t"; break; + case EQ: op = "f"; break; + case NE: op = "t"; break; default: gcc_unreachable (); } } @@ -2148,10 +2113,10 @@ xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) { switch (code) { - case EQ: op = inverted ? "nez" : "eqz"; break; - case NE: op = inverted ? "eqz" : "nez"; break; - case LT: op = inverted ? "gez" : "ltz"; break; - case GE: op = inverted ? "ltz" : "gez"; break; + case EQ: op = "eqz"; break; + case NE: op = "nez"; break; + case LT: op = "ltz"; break; + case GE: op = "gez"; break; default: gcc_unreachable (); } } diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index bf79099f21b..25b8d2fb3c9 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1545,28 +1545,13 @@ (define_insn "*btrue" [(set (pc) (if_then_else (match_operator 3 "branch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "branch_operand" "K,r")]) + [(match_operand:SI 0 "register_operand" "r,r") + (match_operand:SI 1 "branch_operand" "K,r")]) (label_ref (match_operand 2 "" "")) (pc)))] "" { - return xtensa_emit_branch (false, which_alternative == 0, operands); -} - [(set_attr "type" "jump,jump") - (set_attr "mode" "none") - (set_attr "length" "3,3")]) - -(define_insn "*bfalse" - [(set (pc) - (if_then_else (match_operator 3 "branch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "branch_operand" "K,r")]) - (pc) - (label_ref (match_operand 2 "" ""))))] - "" -{ - return xtensa_emit_branch (true, which_alternative == 0, operands); + return xtensa_emit_branch (which_alternative == 0, operands); } [(set_attr "type" "jump,jump") (set_attr "mode" "none") @@ -1575,28 +1560,13 @@ (define_insn "*ubtrue" [(set (pc) (if_then_else (match_operator 3 "ubranch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "ubranch_operand" "L,r")]) + [(match_operand:SI 0 "register_operand" "r,r") + (match_operand:SI 1 "ubranch_operand" "L,r")]) (label_ref (match_operand 2 "" "")) (pc)))] "" { - return xtensa_emit_branch (false, which_alternative == 0, operands); -} - [(set_attr "type" "jump,jump") - (set_attr "mode" "none") - (set_attr "length" "3,3")]) - -(define_insn "*ubfalse" - [(set (pc) - (if_then_else (match_operator 3 "ubranch_operator" - [(match_operand:SI 0 "register_operand" "r,r") - (match_operand:SI 1 "ubranch_operand" "L,r")]) - (pc) - (label_ref (match_operand 2 "" ""))))] - "" -{ - return xtensa_emit_branch (true, which_alternative == 0, operands); + return xtensa_emit_branch (which_alternative == 0, operands); } [(set_attr "type" "jump,jump") (set_attr "mode" "none") @@ -1607,75 +1577,50 @@ (define_insn "*bittrue" [(set (pc) (if_then_else (match_operator 3 "boolean_operator" - [(zero_extract:SI - (match_operand:SI 0 "register_operand" "r,r") - (const_int 1) - (match_operand:SI 1 "arith_operand" "J,r")) - (const_int 0)]) - (label_ref (match_operand 2 "" "")) - (pc)))] - "" -{ - return xtensa_emit_bit_branch (false, which_alternative == 0, operands); -} - [(set_attr "type" "jump") - (set_attr "mode" "none") - (set_attr "length" "3")]) - -(define_insn "*bitfalse" - [(set (pc) - (if_then_else (match_operator 3 "boolean_operator" - [(zero_extract:SI - (match_operand:SI 0 "register_operand" "r,r") - (const_int 1) - (match_operand:SI 1 "arith_operand" "J,r")) + [(zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") + (const_int 1) + (match_operand:SI 1 "arith_operand" "J,r")) (const_int 0)]) - (pc) - (label_ref (match_operand 2 "" ""))))] - "" -{ - return xtensa_emit_bit_branch (true, which_alternative == 0, operands); -} - [(set_attr "type" "jump") - (set_attr "mode" "none") - (set_attr "length" "3")]) - -(define_insn "*masktrue" - [(set (pc) - (if_then_else (match_operator 3 "boolean_operator" - [(and:SI (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "register_operand" "r")) - (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "" { + static char result[64]; + char op; switch (GET_CODE (operands[3])) { - case EQ: return "bnone\t%0, %1, %2"; - case NE: return "bany\t%0, %1, %2"; - default: gcc_unreachable (); + case EQ: op = 'c'; break; + case NE: op = 's'; break; + default: gcc_unreachable (); } + if (which_alternative == 0) + { + operands[1] = GEN_INT (INTVAL (operands[1]) & 0x1f); + sprintf (result, "bb%ci\t%%0, %%d1, %%2", op); + } + else + sprintf (result, "bb%c\t%%0, %%1, %%2", op); + return result; } [(set_attr "type" "jump") (set_attr "mode" "none") (set_attr "length" "3")]) -(define_insn "*maskfalse" +(define_insn "*masktrue" [(set (pc) (if_then_else (match_operator 3 "boolean_operator" - [(and:SI (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "register_operand" "r")) - (const_int 0)]) - (pc) - (label_ref (match_operand 2 "" ""))))] + [(and:SI (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "register_operand" "r")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] "" { switch (GET_CODE (operands[3])) { - case EQ: return "bany\t%0, %1, %2"; - case NE: return "bnone\t%0, %1, %2"; - default: gcc_unreachable (); + case EQ: return "bnone\t%0, %1, %2"; + case NE: return "bany\t%0, %1, %2"; + default: gcc_unreachable (); } } [(set_attr "type" "jump") From patchwork Sun Jun 12 06:38:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55038 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D028F38425B0 for ; Sun, 12 Jun 2022 06:45:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D028F38425B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655016343; bh=Uk8w0egBeu0f2ByhWo15GbhsRxwadfeHAu7QjYq3+GY=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=yNvLsGR+8vSBH7mRZvh7I4ZgIeKMHytCdnaJPoAPHvIF4c3T/bpNhLzOLTR3JWdEJ EHqAEer7+DgyLMt2/DJmY52jC08vwFlNPelnnCAv0HCenHkEz3vu1GI33XHqb+PHtc oX6/iEoPwWQwLz9AcqgO8B+y7DqX76CgrNw8GZnE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh603-vm9.bullet.mail.ssk.yahoo.co.jp (nh603-vm9.bullet.mail.ssk.yahoo.co.jp [182.22.90.50]) by sourceware.org (Postfix) with SMTP id 9F765386F0F6 for ; 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Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH 3/4] xtensa: Make use of BALL/BNALL instructions X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" In Xtensa ISA, there is no single machine instruction that calculates unary bitwise negation, but a few similar fused instructions are exist: "BALL Ax, Ay, label" // if ((~Ax & Ay) == 0) goto label; "BNALL Ax, Ay, label" // if ((~Ax & Ay) != 0) goto label; These instructions have never been emitted before, but it seems no reason not to make use of them. gcc/ChangeLog: * config/xtensa/xtensa.md (*masktrue_bitcmpl): New insn pattern. gcc/testsuite/ChangeLog: * gcc.target/xtensa/BALL-BNALL.c: New. --- gcc/config/xtensa/xtensa.md | 21 +++++++++++++ gcc/testsuite/gcc.target/xtensa/BALL-BNALL.c | 33 ++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 gcc/testsuite/gcc.target/xtensa/BALL-BNALL.c diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 25b8d2fb3c9..090a2939684 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1627,6 +1627,27 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_insn "*masktrue_bitcmpl" + [(set (pc) + (if_then_else (match_operator 3 "boolean_operator" + [(and:SI (not:SI (match_operand:SI 0 "register_operand" "r")) + (match_operand:SI 1 "register_operand" "r")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "" +{ + switch (GET_CODE (operands[3])) + { + case EQ: return "ball\t%0, %1, %2"; + case NE: return "bnall\t%0, %1, %2"; + default: gcc_unreachable (); + } +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "3")]) + ;; Zero-overhead looping support. diff --git a/gcc/testsuite/gcc.target/xtensa/BALL-BNALL.c b/gcc/testsuite/gcc.target/xtensa/BALL-BNALL.c new file mode 100644 index 00000000000..ba61c6f371b --- /dev/null +++ b/gcc/testsuite/gcc.target/xtensa/BALL-BNALL.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +extern void foo(void); + +void BNONE_test(int a, int b) +{ + if (a & b) + foo(); +} + +void BANY_test(int a, int b) +{ + if (!(a & b)) + foo(); +} + +void BALL_test(int a, int b) +{ + if (~a & b) + foo(); +} + +void BNALL_test(int a, int b) +{ + if (!(~a & b)) + foo(); +} + +/* { dg-final { scan-assembler-times "bnone" 1 } } */ +/* { dg-final { scan-assembler-times "bany" 1 } } */ +/* { dg-final { scan-assembler-times "ball" 1 } } */ +/* { dg-final { scan-assembler-times "bnall" 1 } } */ From patchwork Sun Jun 12 06:41:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takayuki 'January June' Suwa X-Patchwork-Id: 55039 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6D66F38418AF for ; Sun, 12 Jun 2022 06:46:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D66F38418AF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1655016407; bh=YqCdh9+CIjvR8nmAyN2laArFJ59oMzG4Epqs1D3AlvE=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=gKdR7v01IWhfoNKFhM+3BN4hCHgo5WLdVZxQyEBFq+zLc0pilruy2QPicekjeA5td nDsi5Jap1wFFvcRGcLQ3DHUNXYIYVYzE+SBT1O1/FEnOCeoicthioxRvlE3HJbmcak 0nmHCw3RIMVegLEdRv/6w4vhogg9g+8I/d+1Fw8E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from nh602-vm5.bullet.mail.ssk.yahoo.co.jp (nh602-vm5.bullet.mail.ssk.yahoo.co.jp [182.22.90.30]) by sourceware.org (Postfix) with SMTP id 26B1B386F0F1 for ; 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(175.177.45.176 with ) by smtp6005.mail.ssk.ynwp.yahoo.co.jp with SMTP; 12 Jun 2022 06:43:19 -0000 X-YMail-JAS: DdivIhoVM1lLCT57qeIvV0LbJSmddvG54lOvk6SIGTFJS8zprIkXB.lB7fhjYNB_F7vA1yPqabg3OtkxUipuDGJINyXFjBFdHCWl6npsiG8JXoyuIfy93QMYPFjbU8d.x3.bx7BSbA-- X-Apparently-From: X-YMail-OSG: 0VCuYMoVM1m0Ns6cYuWtDNuY_egJkoyUP6FrtjKIKp1KEbI 5i5mZClkmoksb1wivtuMGOQzkGvZlrpA14uAwPYwvy79mfjsoOVfqVjJb1GX 8773X8a1MMecMxQucHOYblXcROtHmApHWz2gTsubNKtZiqQo39x1Arec9cKR JmWO_CsE3BPlvAnq9Yb0vHYm21kDswbP5ENPPGXhGkiLBBKS1L3hoxfS3Wcg P9dNlP6FbvFTjGO7ODoucEwdSug7S1uDFU7Bu2b3NeJpVwr8AL6yFf9QL5XV byPEidl6AcKfFDdL6xUJtFYW6.faJWRt9QKUq6gAL2D8SIjMYzDWOglsDp6b dMvx0G3BHDkZsyj5tAcij6efeQLhAwQ2997oF3kqAXqpCSh5bg83WKYYGAzh c.968vDIvFfGJ_VX2zu5mu1pOto.uLhodU3wkD.IPzmVfRb.feYJ9tsKm194 PLgdkafiNhzy15vIp4LFmoDR4BLpUE3H65_7dORysnLwi0OPbf7B85FxmQ.8 THhMYpNy9wBX6uJhmGipKFnNxH3bXigNyaImR8CGF2BwlZboT8q_Z8Idg2If F2.NSyUeJpKn9A0GyoTA_VnNQPQSYzqjX_QuJad3Sm1IDTHqonwBIzbfr9gB SEFGeYrZGgC87SaYaCmJnKOnbngW3YfnOPfqnDlsCAi83YHcn_vjsFzQBXxx GgHaB8LCQSmcvNFgfuk1w2wpXW2sy8xG0FKxxgJtixBd22FU4nyY15pXivAI zTEGQuBIT37fFmRGLWKo6NgGd0O2AjDUIrN9zK3IUGfMOaZOxcB0b8zSKMRA IWxgUXRIfTZduTSKlMBkeyy8uJeYarnpE.EBTo3KlSvCFSsIZ1cK0Vz0sIWH dQwAbV_Ax586MsKpCJBzjqyOR9aGrGkktic4_0VlKLxpEoEHUviFFjX2j2qL ZSZnxE6UyUBpWOZD5yg-- Message-ID: Date: Sun, 12 Jun 2022 15:41:56 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Content-Language: en-US To: GCC Patches Subject: [PATCH 4/4] xtensa: Optimize bitwise AND operation with some specific forms of constants X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch offers several insn-and-split patterns for bitwise AND with register and constant that cannot fit into a "MOVI Ax, simm12" instruction, but can be represented as: i. 1's least significant N bits and the others 0's (17 <= N <= 31) ii. 1's most significant N bits and the others 0's (12 <= N <= 31) iii. M 1's sequence of bits and trailing N 0's bits (1 <= M <= 16, 1 <= N <= 30) And also offers shortcuts for conditional branch if each of the abovementioned operations is (not) equal to zero. gcc/ChangeLog: * config/xtensa/predicates.md (shifted_mask_operand): New predicate. * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): New insn-and-split pattern. (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, *masktrue_const_shifted_mask): Ditto. --- gcc/config/xtensa/predicates.md | 11 +++ gcc/config/xtensa/xtensa.md | 165 ++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index bcc83ada0ae..24c77f343a0 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -52,6 +52,17 @@ (match_test "xtensa_mask_immediate (INTVAL (op))")) (match_operand 0 "register_operand"))) +(define_predicate "shifted_mask_operand" + (and (match_code "const_int") + (match_test "!xtensa_simm12b (INTVAL (op))")) +{ + HOST_WIDE_INT mask = INTVAL (op); + int shift = ctz_hwi (mask); + + return IN_RANGE (shift, 1, 31) + && xtensa_mask_immediate ((uint32_t)mask >> shift); +}) + (define_predicate "extui_fldsz_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 090a2939684..286a1d8c38e 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -645,6 +645,78 @@ (set_attr "mode" "SI") (set_attr "length" "6")]) +(define_insn_and_split "*andsi3_const_pow2_minus_one" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (lshiftrt:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 0x7FFFFFFF") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*andsi3_const_negative_pow2" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)" + "#" + "&& 1" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + +(define_insn_and_split "*andsi3_const_shifted_mask" + [(set (match_operand:SI 0 "register_operand" "=a") + (and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")))] + "" + "#" + "" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 3) + (match_dup 2))) + (set (match_dup 0) + (ashift:SI (match_dup 0) + (match_dup 2)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + operands[2] = GEN_INT (shift); + operands[3] = GEN_INT (floor_log2 (((uint32_t)mask >> shift) + 1)); +} + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && ctz_hwi (INTVAL (operands[2])) == 1") + (const_int 5) + (const_int 6)))]) + (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=a") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -1648,6 +1720,99 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_insn_and_split "*masktrue_const_pow2_minus_one" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (const_int 0)) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "IN_RANGE (INTVAL (operands[2]), 17, 31)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ashift:SI (match_dup 1) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[2] = GEN_INT (32 - INTVAL (operands[2])); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set (attr "length") + (if_then_else (match_test "TARGET_DENSITY + && INTVAL (operands[2]) == 31") + (const_int 5) + (const_int 6)))]) + +(define_insn_and_split "*masktrue_const_negative_pow2" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 30)" + "#" + "&& reload_completed" + [(set (match_dup 0) + (lshiftrt:SI (match_dup 1) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2]))); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + +(define_insn_and_split "*masktrue_const_shifted_mask" + [(set (pc) + (if_then_else (match_operator 4 "boolean_operator" + [(and:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "shifted_mask_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=&a"))] + "" + "#" + "reload_completed" + [(set (match_dup 0) + (zero_extract:SI (match_dup 1) + (match_dup 5) + (match_dup 2))) + (set (pc) + (if_then_else (match_op_dup 4 + [(match_dup 0) + (const_int 0)]) + (label_ref (match_dup 3)) + (pc)))] +{ + HOST_WIDE_INT mask = INTVAL (operands[2]); + int shift = ctz_hwi (mask); + operands[2] = GEN_INT (shift); + operands[5] = GEN_INT (floor_log2 (((uint32_t)mask >> shift) + 1)); +} + [(set_attr "type" "jump") + (set_attr "mode" "none") + (set_attr "length" "6")]) + ;; Zero-overhead looping support.