From 74564292ffd4c0f2baa4d99715cce614dd4572f6 Mon Sep 17 00:00:00 2001
From: Gedare Bloom <gedare@rtems.org>
Date: Thu, 30 Apr 2026 11:10:53 -0600
Subject: [PATCH] riscv: avoid misaligned accesses if __riscv_misaligned_slow

The configure rule for misaligned accesses is too wide by including
__riscv_misaligned_fast or __riscv_misaligned_slow for enabling the
HW supported misaligned access.
---
 newlib/configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/newlib/configure.ac b/newlib/configure.ac
index a4807830e..4640e69c5 100644
--- a/newlib/configure.ac
+++ b/newlib/configure.ac
@@ -555,7 +555,7 @@ if test "x${newlib_hw_misaligned_access}" = "x"; then
   AC_CACHE_CHECK([if $CC has enabled misaligned hardware access],
               [newlib_cv_hw_misaligned_access], [dnl
   cat > conftest.c <<EOF
-#if __riscv_misaligned_fast || __riscv_misaligned_slow
+#if __riscv_misaligned_fast
 void misalign_access_supported(void) {}
 #else
 #error "misaligned access is not supported"
-- 
2.47.3