From patchwork Fri Aug 14 02:26:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pincheng Wang X-Patchwork-Id: 141354 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C54C04BA900F for ; Fri, 14 Aug 2026 02:27:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C54C04BA900F X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 4228A4BA23FF for ; Fri, 14 Aug 2026 02:27:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4228A4BA23FF Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4228A4BA23FF Authentication-Results: sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1786674425; cv=none; b=wZd8ATlmCGMeBI6v2HJFpvqexJnkNbUqB8fhY9LWwY8WwlINOk9OVs7ZClitIjtamABve6oZk4IdNPBilrqmkCnhF2Xk1LWWIGDlPuMGxVgtiUb83iLBK8MGq7QTq39d/siUnuPNcKkSW3HONz5/ad60h8AuCzC7qmcYXkkR45g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1786674425; c=relaxed/simple; bh=i0cCinoCBcWyredKPiFeYGMjSo71oQ+o+qes4wC3eRY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=qPtsVhF2Sm6xnQjEw7gRh7thij9MkiOlHvYs9l+jpMP73QMpXPnZH1UPYG2eZc4uCeMNEEkRKPCk5YPto6U8pxq8EF8ydqfWvhOnUhMZMaQMz5SsFDDpe/nutiSvQFTCGESrEWhFZsJdMc78pOm5i43QqH/bUTnh4hAd14yCQgI= ARC-Authentication-Results: i=1; sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4228A4BA23FF Received: from ROG.localdomain (unknown [183.134.225.12]) by APP-03 (Coremail) with SMTP id rQCowACnsT_xfH5qsxNIBQ--.31342S7; Fri, 14 Aug 2026 10:27:00 +0800 (CST) From: Pincheng Wang To: newlib@sourceware.org Cc: Pincheng Wang Subject: [PATCH v3 05/15] riscv: add vectorized strrchr Date: Fri, 14 Aug 2026 10:26:46 +0800 Message-Id: <20260814022656.1071643-6-pincheng.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260814022656.1071643-1-pincheng.plct@isrc.iscas.ac.cn> References: <20260814022656.1071643-1-pincheng.plct@isrc.iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: rQCowACnsT_xfH5qsxNIBQ--.31342S7 X-Coremail-Antispam: 1UD129KBjvJXoWxGr17Kr4DJr1xWr4DGw4xXrb_yoW5uw18pa nFka1Fy3Wftrn3trn7Xr18urW5Jas3K3W3GFWrAw4UtFsYgayrWFs8tw43Aw4xJryqvF4x u3Wjgr1Y9w15XaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9G14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr 1l84ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2 0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxV W8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbj2MUUUUUU== X-Originating-IP: [183.134.225.12] X-CM-SenderInfo: pslquxhhqjh1xofwqxxvufhxpvfd2hldfou0/ X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_PBL, SPF_HELO_PASS, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org The vector implementation makes a single forward pass, loading each chunk with fault-only-first loads (vle8ff.v) and selecting the highest matching lane index with a masked max-index reduction, so it never crosses into an unmapped page. This provides significant performance improvements on RVV-capable hardware. Use conditional compilation to fall back to the generic implementation when __riscv_vector is not available, maintaining compatibility with non-vector RISC-V systems. Signed-off-by: Pincheng Wang --- newlib/libc/machine/riscv/Makefile.inc | 4 ++- newlib/libc/machine/riscv/strrchr-asm.S | 38 +++++++++++++++++++++++++ newlib/libc/machine/riscv/strrchr.c | 5 ++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 newlib/libc/machine/riscv/strrchr-asm.S create mode 100644 newlib/libc/machine/riscv/strrchr.c diff --git a/newlib/libc/machine/riscv/Makefile.inc b/newlib/libc/machine/riscv/Makefile.inc index 3c13fbc1a..4bb7fefbb 100644 --- a/newlib/libc/machine/riscv/Makefile.inc +++ b/newlib/libc/machine/riscv/Makefile.inc @@ -29,4 +29,6 @@ libc_a_SOURCES += \ %D%/strlen-asm.S \ %D%/strlen.c \ %D%/strnlen-asm.S \ - %D%/strnlen.c + %D%/strnlen.c \ + %D%/strrchr-asm.S \ + %D%/strrchr.c diff --git a/newlib/libc/machine/riscv/strrchr-asm.S b/newlib/libc/machine/riscv/strrchr-asm.S new file mode 100644 index 000000000..1bdb84338 --- /dev/null +++ b/newlib/libc/machine/riscv/strrchr-asm.S @@ -0,0 +1,38 @@ +#include + +#if defined(__riscv_vector) && !defined(__riscv_e) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) +/* char *strrchr(const char *a0, int a1) + Return the last occurrence of (char)a1 in a0, including the terminating + NUL when a1==0, else NULL. Single forward pass: each chunk is loaded with + vle8ff (page-boundary safe) and the highest matching lane index is found + with a masked max-index reduction. */ +ENTRY(strrchr) + li a6, 0 /* result pointer = NULL so far */ +.Lloop: + vsetvli a2, zero, e8, m1, ta, ma + vle8ff.v v8, (a0) + csrr a2, vl + vmseq.vi v1, v8, 0 /* NUL lanes */ + vfirst.m a3, v1 /* first NUL position (or -1) */ + vmseq.vx v2, v8, a1 /* lanes equal to (char)c */ + vmsif.m v3, v1 /* valid lanes: up to & including first NUL */ + vmand.mm v0, v2, v3 /* candidate matches within the string */ + vfirst.m a4, v0 /* any candidate in this chunk? */ + bltz a4, .Lskip + /* reduce the maximum lane index over candidate lanes (need e16 to be + safe for large VLEN where vl can exceed 255). */ + vsetvli zero, a2, e16, m2, ta, ma + vid.v v16 + vmv.s.x v24, x0 + vredmaxu.vs v24, v16, v24, v0.t + vmv.x.s a5, v24 + add a6, a0, a5 +.Lskip: + bgez a3, .Ldone /* reached end of string */ + add a0, a0, a2 + j .Lloop +.Ldone: + mv a0, a6 + ret +END(strrchr) +#endif diff --git a/newlib/libc/machine/riscv/strrchr.c b/newlib/libc/machine/riscv/strrchr.c new file mode 100644 index 000000000..d06b31e4c --- /dev/null +++ b/newlib/libc/machine/riscv/strrchr.c @@ -0,0 +1,5 @@ +#if defined(__OPTIMIZE_SIZE__) || defined(PREFER_SIZE_OVER_SPEED) || !defined(__riscv_vector) || defined(__riscv_e) +# include "../../string/strrchr.c" +#else +/* strrchr defined in strrchr-asm.S */ +#endif