| Message ID | 20260624195835.206509-3-christophe.lyon@arm.com |
|---|---|
| State | New |
| Headers |
Return-Path: <newlib-bounces~patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 742A44BA23D0 for <patchwork@sourceware.org>; Wed, 24 Jun 2026 20:01:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 742A44BA23D0 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BPQ2dYwa; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BPQ2dYwa X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010030.outbound.protection.outlook.com [52.101.69.30]) by sourceware.org (Postfix) with ESMTPS id DC3AE4BA23C7 for <newlib@sourceware.org>; Wed, 24 Jun 2026 20:00:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC3AE4BA23C7 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DC3AE4BA23C7 Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=52.101.69.30 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1782331227; cv=pass; b=QMwCEUwoXhrSk86BxD7ZbLjyH5sIj43Z8q2tkLW7H4t+4ja8NDu1PiRERreNF1k/qVPLeCfTAZlFH51hTdatBKgHLtlTE++uYjccqdil1k9Nylj/jzCIFqYiwTvlm4yaOF4EGGHRfdUWvLPawpaanW5cvAZt8aqvMIF/L8XGHZg= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1782331227; c=relaxed/simple; bh=+HbK9/bVVoUE5lw+/XQhpH2TFRTtOB8NBIMrhfj/75o=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=ZZsKYJK+E7JhVQKkyskUv2wLSX18egj9ARKCv5UPSCTeeYC1knHwpu1LOf1pghW+iesAfj/EV22VDW4wL/saWD+QO+8e0Ilvj12jg+0cWioA4E5RZtbOJkSC+7qT2WwN6Fd3SF8lIqznGUGYGJ/NowsSrVYB19F5dbZn/2w/2A8= ARC-Authentication-Results: i=3; sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BPQ2dYwa; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BPQ2dYwa DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DC3AE4BA23C7 ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=Mv+V8PJtwRo7/MvXX89kRTAVo3GFPvVWlFlQRLL8/sm6wjUjTJuG8L7e2lFLcGNln7slLyJ30QYNGvI8x8GaTSZlCawUinKg32JLW+aendNepfcAKWPHcTwQb6O7ZtLo2evUrVei8+RQFgE4CvDprpDvmjsBdppJx1CXA5yykXVB1M72J8QSdn77QD2709OVLNWvDZvLka23hquuA3UpuiN4wXjQ7YVoDG7XwTz7AC0SljGg4jOiMKnGd4wlw6DFO96bgwydtVvi/AhmoGCY7bzaD6/XdBcn2KGaAXPE0AjMDL8XKvyQIRd81CEA0SQlwPYi3aJCBVKwg2RVWQXN7g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FIc9STo/CtvlygpoTso4CZe+0JurHa7g0Sd/HSZqu0U=; b=ElWEnSkHMruWR9eGpbqWyoGnOCbQOXXZjatzPpDGQ3zBbBWMUQKCee7nbu+JOwqTHYdhcDrlfn2Ufr2OsbPwthOYRjVkiaRVMgwiYXZnqhziLYxPjrvfyEZLjIZoHvjETxOAdymJ0yexFC/cclwKK2nugvF3wAhZ5f857GH67bLIMM4+EemXV1PEg+6ZoI9rvfTrzUH4TsgCu3U4CZT7pNoh2pJbC575BC+cw16XKnNv6eUJeBsKT1SEawX7Ha51Cg8Y2WGc+/McYI8vL6ddTlZ4i83ubQfc4wEmYzKgArWPKwIYcTD847Ccca72PtmhJ8+CKg8ENGC0MHg5C8wUXw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FIc9STo/CtvlygpoTso4CZe+0JurHa7g0Sd/HSZqu0U=; b=BPQ2dYwa8oUT2tpDZgnhkhINUzJgdDERwHgGH/nXIDPb3sZpYO8g6QbpbDKyT/NZwt9HYVp1foJQPk4rQgS5UDWGROHAcY+MBwhsmem1OT7OGXBWYgTIlbrYz4WvBHi/oIhKD6sNSgAnI+DkubFRxBV8uoPb9CL4Ec06Fwvsf2A= Received: from AS4P190CA0027.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:5d0::16) by DB9PR08MB11309.eurprd08.prod.outlook.com (2603:10a6:10:607::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.159.16; Wed, 24 Jun 2026 20:00:15 +0000 Received: from AM4PEPF00027A5E.eurprd04.prod.outlook.com (2603:10a6:20b:5d0:cafe::32) by AS4P190CA0027.outlook.office365.com (2603:10a6:20b:5d0::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.159.16 via Frontend Transport; Wed, 24 Jun 2026 20:00:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AM4PEPF00027A5E.mail.protection.outlook.com (10.167.16.72) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Wed, 24 Jun 2026 20:00:14 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kruc63BmXVlIDHIKNBBcwOlR2aLa++0AX6wrBAYTgj5u6yG7IZ1RCvLdDwkjouDWFFZMcjR/Dpjk39JFqQEbDFpoIQ4mS/lSMhFy6DZBdXJZVczvpSayIQ5E+k7+XV6+seVdDio0VdSppDDwVEZ1enQFgSuma6QghQeTJ3rIozhZscflpCWbUPzJ+U3Zq9jgzOeYKF9UdoJmu6hUrPVP/fFD11ll3J/81RTEuy6rOXnMK+IOBSn70A5elhtit0C0iJ+LZQp1B+c0uZZVHQaTH9UE9IKOR1XRAwG52Wt2s1AVVPbRFVrdsQphIWTqMzbOfDaxsvE+/WRMXmREpunxyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=FIc9STo/CtvlygpoTso4CZe+0JurHa7g0Sd/HSZqu0U=; b=qXYLywe+4WfxDyUJFB3j6a3PMta655OALhz5domoNKDdDOUukoZ46BwLwtY4aRFRs0FQcYypdjEH4tvM85GzwiA5KrqEAmY6sL9sXIYtKgbONH9F7QXANCPAUsoypwTLg3a/3/UEqhhAxfdIqWbBIBS2UXeNwvVpddefF18dkYww2SCGcQrUW9l+UyldQMvCCvjFES8JeBd9o/kNsvMrXI4IyefYr/KhGghHMt5JDGcNlrcDsgXRzMInEKukMpWhr6qcWypgSrp0tnoGeOVDQr6GhfYNwvnKoJj5IyEtmM9/SlWVHd0SxpDcjUv6kXHWsyh9ptLdjBSZGpyEgh08ow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 172.205.89.229) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FIc9STo/CtvlygpoTso4CZe+0JurHa7g0Sd/HSZqu0U=; b=BPQ2dYwa8oUT2tpDZgnhkhINUzJgdDERwHgGH/nXIDPb3sZpYO8g6QbpbDKyT/NZwt9HYVp1foJQPk4rQgS5UDWGROHAcY+MBwhsmem1OT7OGXBWYgTIlbrYz4WvBHi/oIhKD6sNSgAnI+DkubFRxBV8uoPb9CL4Ec06Fwvsf2A= Received: from AS9PR06CA0667.eurprd06.prod.outlook.com (2603:10a6:20b:49c::12) by AS8PR08MB9148.eurprd08.prod.outlook.com (2603:10a6:20b:57f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.159.14; Wed, 24 Jun 2026 19:59:09 +0000 Received: from AM3PEPF0000A799.eurprd04.prod.outlook.com (2603:10a6:20b:49c:cafe::66) by AS9PR06CA0667.outlook.office365.com (2603:10a6:20b:49c::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.159.14 via Frontend Transport; Wed, 24 Jun 2026 19:59:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 172.205.89.229) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 172.205.89.229 as permitted sender) receiver=protection.outlook.com; client-ip=172.205.89.229; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (172.205.89.229) by AM3PEPF0000A799.mail.protection.outlook.com (10.167.16.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Wed, 24 Jun 2026 19:59:09 +0000 Received: from AZ-NEU-EX04.Arm.com (10.240.25.138) by AZ-NEU-EX03.Arm.com (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Wed, 24 Jun 2026 19:59:02 +0000 Received: from e129018.arm.com (10.57.29.173) by mail.arm.com (10.240.25.138) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Wed, 24 Jun 2026 19:59:00 +0000 From: Christophe Lyon <christophe.lyon@arm.com> To: <newlib@sourceware.org> CC: <richard.earnshaw@arm.com>, <andre.simoesdiasvieira@arm.com>, "Christophe Lyon" <christophe.lyon@arm.com> Subject: [PATCH v4 3/3] arm: Enable FPU for M-profile Date: Wed, 24 Jun 2026 21:58:35 +0200 Message-ID: <20260624195835.206509-3-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260624195835.206509-1-christophe.lyon@arm.com> References: <20260624195835.206509-1-christophe.lyon@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM3PEPF0000A799:EE_|AS8PR08MB9148:EE_|AM4PEPF00027A5E:EE_|DB9PR08MB11309:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a483072-89a8-4a47-3513-08ded22b34c5 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|36860700016|82310400026|23010399003|1800799024|376014|18002099003|22082099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info-Original: b+zV0nO5EqAqRx7v0gjviAsY+wkEroQ40n1eWk8z8Zxw2cobQR2w5rLPSGdzF3zw+W1ii5fxW+dA5Kbm2IgjnPNk+biCHz+4Azom2doP2idbBunxMgioocDhNSQWf9QUeaQaXMitcei6vNwJ9cD/mvVYsC78J+x0Ycv/wzXkBFMSfLIKbQ09WPGVp8gssLJXx4qpXth3Ot0Tn/uSQ2MoZuC8Hn4T6v8nINazBrN0B8Psoa99zOp9i7DG5d1o5zAOkpKA/oolOvr61f+6MI6LocaO2ATRw2n3rT9SL6+zKroMqfo0oyxekoGICgQ5xlgKRftZtELFOQ03s195fwJ7n2wqpXxek3CiUV74F5AbzKrPhjF29JIzzQdBZ/JBDbm4aJ1nhpKHrZOn23oDuUVNBwJeSu4gRpCgLHneq0SLN0KIB6prSYd+OEnqATON3eZIgA1fpoWdJmDd30sVqZHffp2KBeOyRtynzTYyZYiIZKyZmMhYRFeULqMKJbS2/GfTjuUEXSesQ/ClQ3HPTsGgzef1phGVhT02iiXkldUKESYmvIoTL0xjXY/RFRATOSvs6Z0lFD1sJpO1EaLIV2Z0TnpafNE47PQbLslpRul6if+pon99VfMgmIHcPTVUd1lfidPldacuBWS4uGAtxNEbSDWNc30dsPtLCAnlH0UXO3C4YJzeHkxZJUyJ3mA1vZZ8tFgUCkG2S8UzZY10hcrtQw== X-Forefront-Antispam-Report-Untrusted: CIP:172.205.89.229; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(23010399003)(1800799024)(376014)(18002099003)(22082099003)(56012099006)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: sbjShmd+v3GrVab7MPfXwJBIbezSl8RpwcpbuiJNLgcPWPXsPvqtchcZje6neJZFsWB2diKCtG+aGXiKcLhbZM0TAv/kBpzRXg8VyxXiVdkQcY1Zyj6ik8YVmsNyVbLrd9qVQfrlSHeKsfUG3csByJKg4wWnfZ3Z+ATXAh8iSiZwl6nau2jdxKpyXwByh4Yk0lZ/wEFOk91ImFDrIyD4+d0wls47zMiK7jWw1EYETHRXZlfM2+nYoMXDMecGcCgGe0e6ro8AqIOQePs3TQcL3eKKfUpQi1mI60w0Tg8+Z4+nOrec8ZAMmpJM3mdc+wsfbA1MkLKBd5qNMDmv2Hlljw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9148 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM4PEPF00027A5E.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 9fe3d726-d13f-4c28-e1ba-08ded22b0e41 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|23010399003|82310400026|1800799024|36860700016|35042699022|14060799003|22082099003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: DPaNP/Wx8ly/zK1q5yO8tXzacRMNzJ/2GKKeZbuALeh3lPfU3+uJrSVFOHKZvPckNWqs1H1tKhz+ERS65vl+pSdNTE4aLF/i2THsjkbdiSqCMtEVmBUIYKX8Jn6J8Elk10F02fLJK5xKm1gCN4YrhDa0V1syh/y7vIP3ifEOzffuwqw2mYc6CrZcHXu1ydYPOrW9/IuufhE+fk+2u1b8ngA4p7wjfWHels3qtNVG824VYgP13yqHFesJQRLcqFFcoVkANtu9ttMCGqpMDRXRIB35luEcYD1r5qZXqXvikzmCmC7Q/Ixg6hp06xwIv4TMMraSxMlZXhctPHW5kpkApqFkL2d7WPbDG8A5Fu9wtfXuyWD/p36nrwstgqxejqeje2kIYolfECns/yKVzhMU04dFzp5Zj2goK2iXdveuCn6bFdd3O+1/qlcK96YRbUFcDkJTlNHzFesFGJx4Ar5Xw1lUcsYy7k6nqW5qa+SRkIwq8f8OdzJEN9HLoVYMGRdB8cEPIAXfdxsDNTkNp0kxSnjmLdIAQ2ID0U5EFMFtfJyr2gTwS0JtLu8eS0xYULzskcon62LyLjH//WhYyLPSvg/C8OquxldfcuyaoEsXDXh8Oo7F61I122Mo9Tl6N0wGIG7qb7tgC1kK/NFEEDujBfzEMft4DFq1elDIYDX6+kVPBQp2Aw8ok7J8rW/McYj57iQy9Mai6qWmtStg4KAaWA== X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(23010399003)(82310400026)(1800799024)(36860700016)(35042699022)(14060799003)(22082099003)(18002099003)(11063799006)(56012099006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oDvyh7dU/Tezzztbf72Tfxf4LCTr+uxcPIiHjCxRqtNW4wI3hkxOD3a5AKV6G0D14ZNHi9qbfck80rydqd4ID2rMGL8l28zL8pKABgq0X/QiTgv8qKwj8I6l/zoKi0fpOi4+hwWXYPfyweNaJb0iWZNAa1RPdrVzZ6fe70aMt06nXowsBPAzRKjimosjMFvhJrP7s5QHupUnS1S7IU9Bh72LS0rgrcuxDrNMPSFVBhFOjYgsfGWGvNjrORN9wvCXcOZDq8np5B1QZk37y7biQOOSDkiuY23ambBlTZQzISKKQr6KwvKM7Uyu8SEGv/1x0ld8Wg3SxItbndT3PSXk/RFN947HRNDTJWrQQDoXWaArHjVpRxFL5+3YFlyUO/erJiecr6bnaH7IrFwCSZyEkVYIDdJ896fzZpSx50utmY7bXIgkqc0wsWV79DPk+SQr X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2026 20:00:14.3664 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a483072-89a8-4a47-3513-08ded22b34c5 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A5E.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB11309 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list <newlib.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/newlib>, <mailto:newlib-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/newlib/> List-Post: <mailto:newlib@sourceware.org> List-Help: <mailto:newlib-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/newlib>, <mailto:newlib-request@sourceware.org?subject=subscribe> Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org |
| Series |
[v4,1/3] libgloss: arm: Reorganize rdimon-aem.S
|
|
Commit Message
Christophe Lyon
June 24, 2026, 7:58 p.m. UTC
Before using the FPU, we must grant access to it. This helps when running the GCC testsuite on a simulator where FPU access is not granted by default. This patch grants full access, we may want to consider granting only unprivileged access later. While updating crt0.S, include arm-acle-compat.h and stop using __ARM_ARCH_7A__. 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> * libgloss/arm/cpu-init/rdimon-aem-m.S: Enable full FPU access on M-profile. * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile too. --- libgloss/arm/cpu-init/rdimon-aem-m.S | 29 +++++++++++++++++++++++++++- libgloss/arm/crt0.S | 9 +++------ 2 files changed, 31 insertions(+), 7 deletions(-)
Comments
On 2026-06-24 21:58, Christophe Lyon wrote: > Before using the FPU, we must grant access to it. This helps when > running the GCC testsuite on a simulator where FPU access is not > granted by default. > > This patch grants full access, we may want to consider granting only > unprivileged access later. > > While updating crt0.S, include arm-acle-compat.h and stop using > __ARM_ARCH_7A__. > > 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> > > * libgloss/arm/cpu-init/rdimon-aem-m.S: Enable full FPU access on > M-profile. > * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile > too. > --- > libgloss/arm/cpu-init/rdimon-aem-m.S | 29 +++++++++++++++++++++++++++- > libgloss/arm/crt0.S | 9 +++------ > 2 files changed, 31 insertions(+), 7 deletions(-) > > diff --git a/libgloss/arm/cpu-init/rdimon-aem-m.S b/libgloss/arm/cpu-init/rdimon-aem-m.S > index 611849077..c495efc2d 100644 > --- a/libgloss/arm/cpu-init/rdimon-aem-m.S > +++ b/libgloss/arm/cpu-init/rdimon-aem-m.S > @@ -28,9 +28,36 @@ > We define a hardfault handler, required to prevent the simulator > from entering into an infinite loop. This handler is located at > address 0xc by default when linking with mprofile-mps2.specs which > - uses --section-start=.hardfault_handler_addr=0xc. */ > + uses --section-start=.hardfault_handler_addr=0xc. > + > + Enable the FPU when __ARM_FP is set. */ > > #if (__ARM_ARCH_PROFILE == 'M') > + .syntax unified > + .thumb > + > + @ CPU Initialisation > + .globl _rdimon_hw_init_hook > + .type _rdimon_hw_init_hook, %function > + > +_rdimon_hw_init_hook: > + /* Enable FPU for M-profile only . */ > +#if __ARM_FP > + /* Read CPACR */ > + ldr r0, =0xE000ED88 > + ldr r1, [R0] > + /* Enable full access to CP10 and CP11. */ > + orr r1, r1, #(0xFF << 20) > + str r1, [R0] > +#if __ARM_ARCH >= 800 > + ldr r0, =0xE002ED88 > + str r1, [R0] Is this okay to do? Are we sure that this rdimon-aem-m.S is never included in a non-secure application? What happens if it is included in a non-secure application, secure fault? Kind regards, Torbjörn > +#endif > + dsb > + isb > +#endif > + bx lr > + > /* On M-profile, call abort in case of hardfault: this causes the > simulator to abort execution instead of going into an infinite > loop. */ > diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S > index b9e768007..cad002d2b 100644 > --- a/libgloss/arm/crt0.S > +++ b/libgloss/arm/crt0.S > @@ -1,6 +1,7 @@ > #include "newlib.h" > #include "arm.h" > #include "swi.h" > +#include "arm-acle-compat.h" > > /* ANSI concatenation macros. */ > #define CONCAT(a, b) CONCAT2(a, b) > @@ -250,12 +251,8 @@ > FUNC_START _start > FN_EH_START > > - /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A > - has been defined since 4.2 onwards, which is when v7-a support was added > - and hence 'A' profile support was added in the compiler. Allow for this > - file to be built with older compilers. We only call this for A profile > - cores. */ > -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') > + /* We only call this for A and M profile cores. */ > +#if (__ARM_ARCH_PROFILE == 'A') || (__ARM_ARCH_PROFILE == 'M') > /* The init hook does not use the stack and is called before the stack has been set up. */ > #ifdef ARM_RDI_MONITOR > bl _rdimon_hw_init_hook
On 6/25/26 21:08, Torbjorn SVENSSON wrote: > > > On 2026-06-24 21:58, Christophe Lyon wrote: >> Before using the FPU, we must grant access to it. This helps when >> running the GCC testsuite on a simulator where FPU access is not >> granted by default. >> >> This patch grants full access, we may want to consider granting only >> unprivileged access later. >> >> While updating crt0.S, include arm-acle-compat.h and stop using >> __ARM_ARCH_7A__. >> >> 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> >> >> * libgloss/arm/cpu-init/rdimon-aem-m.S: Enable full FPU access on >> M-profile. >> * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile >> too. >> --- >> libgloss/arm/cpu-init/rdimon-aem-m.S | 29 +++++++++++++++++++++++++++- >> libgloss/arm/crt0.S | 9 +++------ >> 2 files changed, 31 insertions(+), 7 deletions(-) >> >> diff --git a/libgloss/arm/cpu-init/rdimon-aem-m.S b/libgloss/arm/cpu- >> init/rdimon-aem-m.S >> index 611849077..c495efc2d 100644 >> --- a/libgloss/arm/cpu-init/rdimon-aem-m.S >> +++ b/libgloss/arm/cpu-init/rdimon-aem-m.S >> @@ -28,9 +28,36 @@ >> We define a hardfault handler, required to prevent the simulator >> from entering into an infinite loop. This handler is located at >> address 0xc by default when linking with mprofile-mps2.specs which >> - uses --section-start=.hardfault_handler_addr=0xc. */ >> + uses --section-start=.hardfault_handler_addr=0xc. >> + >> + Enable the FPU when __ARM_FP is set. */ >> #if (__ARM_ARCH_PROFILE == 'M') >> + .syntax unified >> + .thumb >> + >> + @ CPU Initialisation >> + .globl _rdimon_hw_init_hook >> + .type _rdimon_hw_init_hook, %function >> + >> +_rdimon_hw_init_hook: >> + /* Enable FPU for M-profile only . */ >> +#if __ARM_FP >> + /* Read CPACR */ >> + ldr r0, =0xE000ED88 >> + ldr r1, [R0] >> + /* Enable full access to CP10 and CP11. */ >> + orr r1, r1, #(0xFF << 20) >> + str r1, [R0] >> +#if __ARM_ARCH >= 800 >> + ldr r0, =0xE002ED88 >> + str r1, [R0] > > Is this okay to do? > Are we sure that this rdimon-aem-m.S is never included in a non-secure > application? What happens if it is included in a non-secure application, > secure fault? > Hi Torbjorn, We can't quite ever be sure of how bootcode is used, the onus is on the developer to make sure they have the appropriate bootcode for their application. To be clear, this bootcode is only used when the user specifies --specs=mprofile-mps2.specs. The fact is that all M-profile cores boot in a mode for which, if FP is present, the registers we write to here are accessible, regardless of whether CMSE is available or not. In other words, the more general use-case for AEM models emulating MPS2 M-profile CPUs is covered. The only concern is if a user uses this bootcode to build an image that is loaded onto non-secure memory, with FPU enabled. In that case there HAS to be another image that is loaded onto secure and calls into the entry point for the non-secure image, it also requires some setup on the secure side for the non-secure code to boot. All this requires a non-standard linker script and more complex bootcode. All this to say, the user needs to be well aware of what they are doing and they should know not to use this bootcode for that scenario as it will never work. One could also argue that this bootcode is used when the user specifies --specs=aprofile*.specs but is actually targeting M-profile: again, the user needs to be aware of what they are doing. Thanks, Christophe > Kind regards, > Torbjörn > >> +#endif >> + dsb >> + isb >> +#endif >> + bx lr >> + >> /* On M-profile, call abort in case of hardfault: this causes the >> simulator to abort execution instead of going into an infinite >> loop. */ >> diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S >> index b9e768007..cad002d2b 100644 >> --- a/libgloss/arm/crt0.S >> +++ b/libgloss/arm/crt0.S >> @@ -1,6 +1,7 @@ >> #include "newlib.h" >> #include "arm.h" >> #include "swi.h" >> +#include "arm-acle-compat.h" >> /* ANSI concatenation macros. */ >> #define CONCAT(a, b) CONCAT2(a, b) >> @@ -250,12 +251,8 @@ >> FUNC_START _start >> FN_EH_START >> - /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however >> __ARM_ARCH_7A >> - has been defined since 4.2 onwards, which is when v7-a support >> was added >> - and hence 'A' profile support was added in the compiler. Allow >> for this >> - file to be built with older compilers. We only call this for A >> profile >> - cores. */ >> -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') >> + /* We only call this for A and M profile cores. */ >> +#if (__ARM_ARCH_PROFILE == 'A') || (__ARM_ARCH_PROFILE == 'M') >> /* The init hook does not use the stack and is called before the >> stack has been set up. */ >> #ifdef ARM_RDI_MONITOR >> bl _rdimon_hw_init_hook >
diff --git a/libgloss/arm/cpu-init/rdimon-aem-m.S b/libgloss/arm/cpu-init/rdimon-aem-m.S index 611849077..c495efc2d 100644 --- a/libgloss/arm/cpu-init/rdimon-aem-m.S +++ b/libgloss/arm/cpu-init/rdimon-aem-m.S @@ -28,9 +28,36 @@ We define a hardfault handler, required to prevent the simulator from entering into an infinite loop. This handler is located at address 0xc by default when linking with mprofile-mps2.specs which - uses --section-start=.hardfault_handler_addr=0xc. */ + uses --section-start=.hardfault_handler_addr=0xc. + + Enable the FPU when __ARM_FP is set. */ #if (__ARM_ARCH_PROFILE == 'M') + .syntax unified + .thumb + + @ CPU Initialisation + .globl _rdimon_hw_init_hook + .type _rdimon_hw_init_hook, %function + +_rdimon_hw_init_hook: + /* Enable FPU for M-profile only . */ +#if __ARM_FP + /* Read CPACR */ + ldr r0, =0xE000ED88 + ldr r1, [R0] + /* Enable full access to CP10 and CP11. */ + orr r1, r1, #(0xFF << 20) + str r1, [R0] +#if __ARM_ARCH >= 800 + ldr r0, =0xE002ED88 + str r1, [R0] +#endif + dsb + isb +#endif + bx lr + /* On M-profile, call abort in case of hardfault: this causes the simulator to abort execution instead of going into an infinite loop. */ diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index b9e768007..cad002d2b 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -1,6 +1,7 @@ #include "newlib.h" #include "arm.h" #include "swi.h" +#include "arm-acle-compat.h" /* ANSI concatenation macros. */ #define CONCAT(a, b) CONCAT2(a, b) @@ -250,12 +251,8 @@ FUNC_START _start FN_EH_START - /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A - has been defined since 4.2 onwards, which is when v7-a support was added - and hence 'A' profile support was added in the compiler. Allow for this - file to be built with older compilers. We only call this for A profile - cores. */ -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') + /* We only call this for A and M profile cores. */ +#if (__ARM_ARCH_PROFILE == 'A') || (__ARM_ARCH_PROFILE == 'M') /* The init hook does not use the stack and is called before the stack has been set up. */ #ifdef ARM_RDI_MONITOR bl _rdimon_hw_init_hook