| Message ID | 20260619130401.130409-1-christophe.lyon@arm.com |
|---|---|
| State | New |
| Headers |
Return-Path: <newlib-bounces~patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 915D84BAE7D1 for <patchwork@sourceware.org>; Fri, 19 Jun 2026 13:06:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 915D84BAE7D1 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=Omaq1m1w; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=Omaq1m1w X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013067.outbound.protection.outlook.com [40.107.162.67]) by sourceware.org (Postfix) with ESMTPS id 3229A4BA799F for <newlib@sourceware.org>; Fri, 19 Jun 2026 13:05:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3229A4BA799F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3229A4BA799F Authentication-Results: sourceware.org; arc=pass smtp.remote-ip=40.107.162.67 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1781874321; cv=pass; b=NiMi/FqbLcSdrEHNTse0t5teApi9bH9SfVTMNy2y26/ajIkAMJAWDu4GuiSbFkmCzvalKJhVUj9c3qcwyNuhEyhoCTDmIh24BoeyuT+T5faNzD79kLRZwf1sf0b6ALazIAQN3M1W/JIJ4QsDbf/id6DG2OCqmXeT4+pU4GNGBpY= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1781874321; c=relaxed/simple; bh=pP5a1cEVNeYGVXgkIIu5iqaf0U1U/WpdD/BZ3BzZBoI=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=EhHbxSVAXgFM2ZRGkUO8L0+fE0ttQeZHWKkUzyjHunbSjg8VEB4Ca32oOW1ZT5ld4qYkGHgkDmbRmw6uRTR8VKQQYCVN18+Bmqaf133fSWQzxaZQOrB2c6l8IXS+vingc6Y6ZZNCSK7B1R8+sOPZC7aFRzOkYHStw1HIMO1VUhc= ARC-Authentication-Results: i=3; sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=Omaq1m1w; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=Omaq1m1w DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3229A4BA799F ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=pass; b=YXdr4DvFW9khuNZ0SS6qMuuE2IsxBhG1Ose8VBfcSEUeqguwTGZNIwWLOz9sln94i5UkplVjfoc/MSb+dyecl1S3guZCuP8kJN4aMvbGAGi4+ebx9uE9fsjF8XhnqQ/T/chsMN6GWp/zG4OizBQYTTChER+Tg6fkn78uHZVGZjH7x/O8NpCyr7YVmyDdgiGimPIP5wdkhFbfcOQez65gGV7CRL+O4fDL4BEOyuI6rxVfJco1RvNxxDwo1ZJpV7SpPRK26jOzpWyUkyYvnrMUY3q/su5vK0SAUSHQ7ZsI6cZ/maz3bV41R9bU9cplmUoOvFbwl8r0AGBJNbM5N/e+Uw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MPhGmcoKHU58mBUckyWHQLo5EILyFuvJzENqiKd6Ius=; b=xGCQh5jrs4pzqTd6B2dOr2OFWVRAKvsWD2s6qYyUTISmNZUs6Gal1NQ4fl5z1PFk03Tru0WyOhyKbOoggETPi9i+jKC4w1H3XF1qg0LGe/a4TVD/TnkyV41f7kgn7R359u6mfjhCUrMrU/WuHphhMcxT9drZ5de4ggr6bEzOIzYxCRqxBszpQP+zRuNsVqkc/toTUasb4o3vaDsHL0QOIM+x9DvGwv9JwdU+UHo0/fOSK7aThbKx3sumLtzPW7GPJHyBRIk2oU9tClKk34dPxWRhH+MCpKkuApiEZ33rK3rJnNXSrQbxSN3xKJJWvwkDFq2wjKB2M+diidfrahJuCg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MPhGmcoKHU58mBUckyWHQLo5EILyFuvJzENqiKd6Ius=; b=Omaq1m1w0wUIrJ+o5Qb1vNPEJ8i/RxIDT5fGqpw0kYlWoJ2ghefMbGgEgJK63YfRL8kNT/8uMnwYlhaYIjC2A0pfAq0e2kdmp3SiuLWr+s8I2DdbJOvguTNaf3v5UzC2FDoj8T3G5y0lqs5hcyFdXpkx3jhUtx5qqDO1nJHdGbw= Received: from CW1P123CA0001.GBRP123.PROD.OUTLOOK.COM (2603:10a6:400:293::9) by PAVPR08MB9377.eurprd08.prod.outlook.com (2603:10a6:102:302::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.139.13; Fri, 19 Jun 2026 13:05:13 +0000 Received: from AMS1EPF00000092.eurprd05.prod.outlook.com (2603:10a6:400:293:cafe::97) by CW1P123CA0001.outlook.office365.com (2603:10a6:400:293::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.71.16 via Frontend Transport; Fri, 19 Jun 2026 13:05:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AMS1EPF00000092.mail.protection.outlook.com (10.167.242.89) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.139.8 via Frontend Transport; Fri, 19 Jun 2026 13:05:12 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fsifuRUaDtvi9DM9Vea0sPECiMHaWcKyQRF+23lCmNG5PAqNiyBStdIMihxi5sTg+SPymLW5z2sNmqZbwbD6rFzrDnVzOrRQ+K4ZoPzOlQFI8igpCME60nPACVuEgy2BuXK3CFJgPk5GZTmuT1GZ1Hb/QArUTvMJn80npwDcmawIZzQkFIsHIiYMljrAXzMlLA8X+7eGOyNDbbFcYl+opVwaAOiNSoKcHLamV7uIohIzCEupiVUtSLm72/WirKrV2KAMepK5rWdgYKQcWJUbFlqyrZlM9+Tde91yd6TO2ByH5Ca8ko+moV6uGJrm1mezBDQqRtrfDrz0NvD8vJzYDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MPhGmcoKHU58mBUckyWHQLo5EILyFuvJzENqiKd6Ius=; b=ZacvgMP6HJGaQqbxwURyN4JeJ5aVvDAYF/vt+tjWvY1eA5X+T68D3ay2AcYmWqo+3in82prAVPYfMF+HBRba6ObnuN6vWrPoMebwBt/bJDXdFVoxspgdjMXcrbu+O2C3NwQPVTV9N5BhlwRbkdm6FaZxQw63zBdYKCjYq9TyuzhsWiaNemY7ALasCwTXd5zMqqb2MJsojLaSAtLcpEYauT1L6BlFQvK16pLwrcUFZB343Pd2guKCJpSFQVwWY4is+Amzci5ynb1Sjg9yfRDPcQfG6YRPi6Dv745hIqVUbJxSvs/iWZOgw30yWz3feDxEClWyJ9yB9zcZnBclEMgylg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 172.205.89.229) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MPhGmcoKHU58mBUckyWHQLo5EILyFuvJzENqiKd6Ius=; b=Omaq1m1w0wUIrJ+o5Qb1vNPEJ8i/RxIDT5fGqpw0kYlWoJ2ghefMbGgEgJK63YfRL8kNT/8uMnwYlhaYIjC2A0pfAq0e2kdmp3SiuLWr+s8I2DdbJOvguTNaf3v5UzC2FDoj8T3G5y0lqs5hcyFdXpkx3jhUtx5qqDO1nJHdGbw= Received: from AS9PR06CA0167.eurprd06.prod.outlook.com (2603:10a6:20b:45c::19) by AM0PR08MB5315.eurprd08.prod.outlook.com (2603:10a6:208:18e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.139.11; Fri, 19 Jun 2026 13:04:08 +0000 Received: from AM4PEPF00027A64.eurprd04.prod.outlook.com (2603:10a6:20b:45c:cafe::1) by AS9PR06CA0167.outlook.office365.com (2603:10a6:20b:45c::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.139.16 via Frontend Transport; Fri, 19 Jun 2026 13:04:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 172.205.89.229) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 172.205.89.229 as permitted sender) receiver=protection.outlook.com; client-ip=172.205.89.229; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (172.205.89.229) by AM4PEPF00027A64.mail.protection.outlook.com (10.167.16.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.139.8 via Frontend Transport; Fri, 19 Jun 2026 13:04:08 +0000 Received: from AZ-NEU-EX03.Arm.com (10.240.25.137) by AZ-NEU-EX03.Arm.com (10.240.25.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Fri, 19 Jun 2026 13:04:05 +0000 Received: from e129018.arm.com (10.57.25.236) by mail.arm.com (10.240.25.137) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Fri, 19 Jun 2026 13:04:05 +0000 From: Christophe Lyon <christophe.lyon@arm.com> To: <newlib@sourceware.org> CC: <richard.earnshaw@arm.com>, <andre.simoesdiasvieira@arm.com>, "Christophe Lyon" <christophe.lyon@arm.com> Subject: [PATCH v3] arm: Enable FPU for M-profile Date: Fri, 19 Jun 2026 15:04:01 +0200 Message-ID: <20260619130401.130409-1-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00027A64:EE_|AM0PR08MB5315:EE_|AMS1EPF00000092:EE_|PAVPR08MB9377:EE_ X-MS-Office365-Filtering-Correlation-Id: 97cac2ee-1aad-406a-433c-08dece03664e x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|82310400026|376014|1800799024|23010399003|36860700016|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info-Original: t6HEHTKsXMM73cfHaR0IzaDbR3OyvoTqgsIcAaB/ezWFsVcdgtN7hCB0lJTGr4+Ga0n5XuteerLfKyQDCMSrxcwzYHvFU9kXo6UAUMLrmSOveGx5U16tSAWye7USKeP2I8yJUAFqQV6NzMd2Yi4jEzrrRrkmc1Qsl+qZEZNYYfnj7ZiYVtvHeb6sS4IWdM7sHwJAUr7lr1WYetLrpyYtxOOT2EFqOgaAxX1yi9N1FAgiWH9LPeaNWitSFxjNuaXcop+i5UPKbqc4z89rgk1RTt1OU/mxSHNyUccKnI9Wcj644AD1cFqeBcTs+dHTSeMh18P4GWm4C07tX47YZ2YplruK6RXFrFWAJWzyVrBbU8EI144V/s/RRKEjfkE8GmY/f2bG1Qgz/KU5zvh1sdm/WCk0ooIHezFodWTFrFa6bhzp9BCe83EwdEL5BeXlJE9pWgetmaPDUvHHnDuPm/noYr4DQim1CZUt/PD2n367jgSyOHodg4ahG7hbEmox4oEKnecjWr0i4e1QhsIKz3W6oC648DpeIptFv0G8AZ1Yt5y6BzhKrUD7x/IBtXINa/bO2YigYtONfPlnElCJawF8xQbfWd0/ZZ6J8peuAHy1NCx2X+8fG9uh5MB72OIJ6mQlIVLPDUVopKK5pptzodkjTWwI27okR8mDxzVvy3GVy914eFzVbUhGE1a1JUJfHHhM5A2ykzRQLDlljPQ8hQND4w== X-Forefront-Antispam-Report-Untrusted: CIP:172.205.89.229; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(23010399003)(36860700016)(18002099003)(56012099006)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: f0R0M8mxd6msaHu4wMz5Iu9czAJ7HXCfHRi1yb1VKQ0Jts+H4r/GzybUXwgluCtm6IniJqXFEXwgNpecMzO9rVDWLeRkNdMiXr2qBhD8WyhquKpfOfu4ezh1/wEc0Qz1exxS0C2jeqETKQfOUwutgzG6Gvg0GrsDwz9cTB5/HNukIVr5hhXM7z3RaxGvzseHYxeUzBl0NjJ6n8RAATZ3CwxXhG4oCEXqqwcmXoWrc3/QTpkOj1yWSZWY1YVDh9IVYnn98erNNU1M/OYqubbP9yT1EJreFLf+9uwI+h0wYqf2PiIgFNP036HcAS82FJbT1jbyjeFGw7+w8kQgqIKDjQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5315 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AMS1EPF00000092.eurprd05.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 58ab0ba0-e49d-48c8-18e3-08dece033fc0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|1800799024|14060799003|376014|35042699022|23010399003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: GFMolbg1ohffUeUeMynJCZpNrdZyjgNWvnQADDz9Gx6JETnBEmrRUYd/GUrjUYh1QoDT50Oqlw0n4qIkUJM0LNTDgevKG3BuyYqbeAzqxjCkJirNw3jlXdokJg5d77RpL/rCDiA+MS1zuaGf1znBKKNNm2Phwoq06JGlQgsPjDegQx5zSxJL7GS++q1U1ziF0e4IHskO88+bfGkyhtcKTsuFxGrB4EWkza2WRX1PlbyrcJs4zOWplV4RFTn+1NMTdSWZSzMYkcN4co1ct+sujcl8w5fD+x0NsCi3srZ5HFWcHvvpWEvWVEIVPv/BgiqrPYNSnbaVaLFXY0Mc2AhqZf8VgeWvM3xGK30GclW2w8wjJFrrNqXbb3eA0BY1fVH5Hy8EDK39Uj6jJ8YbMeJhXaAejsjDIhz50zgLS4i8XYYF9iea8nfXWEyeL7pdZXi2LnGRt+SJcdW1ovTITXbnSKj9Gh3YdB0nwkfYwZPqN4J76X38Qr3xpeNDCn27s2/BIpoWG1sy8hRYwT0iO7345hQUf2Iux02UE4mpeH+6oDa/8XVMXU5bYin8i00AaOdt5akJ0utIxmJx3zywJdSBu4IQBQtKCAEaXsyy+58iY+UgqcyF40wpVAu7i2cbV5dJrPusKnO4RteiHnlYqiu5yxw/7bEhYG8AJVomumHXYgldyz9XOYsS0iM2SquTM1rN7GPPDryKL74+IFRVjhZuCg== X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(1800799024)(14060799003)(376014)(35042699022)(23010399003)(18002099003)(56012099006)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6Ad6pxgEHL8sV0m5ouMJIEDGbLqWFGG0DVY0y76B+pVuLIe1tchsoVs7BiP34KcGnWhFiH9Wc40ScIUPN+v3nd+VwIeoIjry7FwGP+nsDczta3jdCDLqGfllmfzGrKRXC/WQcgNF/tfIARzSFCoGJyxiT33SLh0vBcGkIokgB6B2aj/wO2XU78MDornjzyao3EcloMmKHQsLYnSheEEcVqTm3EtJgNNP/ZnLDWyMN2iUMzear6S4y+gCu53sYyR9flBVlH7bZtE7npj20WOMxpkiKziR/yrdsatAg0AweqktrdX6vvbpORTf/dmdcekRDstdv7ydAOFU4cfOg9WijvjPRTTnKb+poiUTcxgXOmLTcgK2+icneBSFmFRVlZnAg3cUgxDV/RKPhCV/WuhDzbobFfrR86IRno8Glsx06pgryVTNpQeVWbnZkxpePHmx X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2026 13:05:12.9466 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97cac2ee-1aad-406a-433c-08dece03664e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000092.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9377 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list <newlib.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/newlib>, <mailto:newlib-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/newlib/> List-Post: <mailto:newlib@sourceware.org> List-Help: <mailto:newlib-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/newlib>, <mailto:newlib-request@sourceware.org?subject=subscribe> Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org |
| Series |
[v3] arm: Enable FPU for M-profile
|
|
Commit Message
Christophe Lyon
June 19, 2026, 1:04 p.m. UTC
Before using the FPU, we must grant access to it. This helps when running the GCC testsuite on a simluator where FPU access is not granted by default. This patch grants full access, we may want to consider granting only unpriviledged access later. 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> * libgloss/arm/cpu-init/rdimon-aem.S: Enable full FPU access on M-profile. * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile too. --- libgloss/arm/cpu-init/rdimon-aem.S | 28 +++++++++++++++++++++++++--- libgloss/arm/crt0.S | 4 ++-- 2 files changed, 27 insertions(+), 5 deletions(-)
Comments
On 19/06/2026 14:04, Christophe Lyon wrote: > Before using the FPU, we must grant access to it. This helps when > running the GCC testsuite on a simluator where FPU access is not > granted by default. > > This patch grants full access, we may want to consider granting only > unpriviledged access later. > > 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> > > * libgloss/arm/cpu-init/rdimon-aem.S: Enable full FPU access on > M-profile. > * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile > too. > --- > libgloss/arm/cpu-init/rdimon-aem.S | 28 +++++++++++++++++++++++++--- > libgloss/arm/crt0.S | 4 ++-- > 2 files changed, 27 insertions(+), 5 deletions(-) > > diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu-init/rdimon-aem.S > index c960924d4..c8640632a 100644 > --- a/libgloss/arm/cpu-init/rdimon-aem.S > +++ b/libgloss/arm/cpu-init/rdimon-aem.S > @@ -25,9 +25,10 @@ > > /* This file gives a basic initialisation of a Cortex-A series core. It is > the bare minimum required to get Cortex-A core running with a semihosting > - interface. For M-profile we only define a hardfault handler, required to > - prevent the simulator from entering into an infinite loop. The comments > - below apply to A-profile only. > + interface. For M-profile we define a hardfault handler, required to > + prevent the simulator from entering into an infinite loop and we enable > + the FPU when __ARM_FP is set. > + The comments below apply to A-profile only. > Isn't this comment part of your other patch series? > It sets up a basic 1:1 phsyical address to virtual address mapping; > turns the MMU on; enables branch prediction; activates any integrated > @@ -542,6 +543,27 @@ page_tables: > PT7(0x1c0e) > > #elif (__ARM_ARCH_PROFILE == 'M') > + .syntax unified > + .thumb > + > + @ CPU Initialisation > + .globl _rdimon_hw_init_hook > + .type _rdimon_hw_init_hook, %function > + > +_rdimon_hw_init_hook: > + /* Enable FPU for M-profile only . */ > +#if __ARM_FP > + /* Read CPACR */ > + ldr r0, =0xE000ED88 > + ldr r1, [R0] > + /* Enable full access to CP10 and CP11. */ > + orr r1, r1, #(0xFF << 20) > + str r1, [R0] > + dsb > + isb What about the NS version of this register (@0xE002ED88) when starting in secure state? Even if we don't want to set it here, I think we should note that in a comment and explain why. > +#endif > + bx lr > + > /* On M-profile, call abort in case of hardfault: this causes the simulator to > abort execution instead of going into an infinite loop. */ > .section .hardfault_handler_addr, "a" > diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S > index b9e768007..d355405e3 100644 > --- a/libgloss/arm/crt0.S > +++ b/libgloss/arm/crt0.S > @@ -253,9 +253,9 @@ > /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A > has been defined since 4.2 onwards, which is when v7-a support was added > and hence 'A' profile support was added in the compiler. Allow for this > - file to be built with older compilers. We only call this for A profile > + file to be built with older compilers. We only call this for A and M profile > cores. */ > -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') > +#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') || (__ARM_ARCH_PROFILE == 'M') We should include arm-acle-compat.h and drop the __ARM_ARCH_7A__ test now. > /* The init hook does not use the stack and is called before the stack has been set up. */ > #ifdef ARM_RDI_MONITOR > bl _rdimon_hw_init_hook R.
On 6/22/26 13:08, Richard Earnshaw wrote: > On 19/06/2026 14:04, Christophe Lyon wrote: >> Before using the FPU, we must grant access to it. This helps when >> running the GCC testsuite on a simluator where FPU access is not >> granted by default. >> >> This patch grants full access, we may want to consider granting only >> unpriviledged access later. >> >> 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> >> >> * libgloss/arm/cpu-init/rdimon-aem.S: Enable full FPU access on >> M-profile. >> * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile >> too. >> --- >> libgloss/arm/cpu-init/rdimon-aem.S | 28 +++++++++++++++++++++++++--- >> libgloss/arm/crt0.S | 4 ++-- >> 2 files changed, 27 insertions(+), 5 deletions(-) >> >> diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu- >> init/rdimon-aem.S >> index c960924d4..c8640632a 100644 >> --- a/libgloss/arm/cpu-init/rdimon-aem.S >> +++ b/libgloss/arm/cpu-init/rdimon-aem.S >> @@ -25,9 +25,10 @@ >> /* This file gives a basic initialisation of a Cortex-A series >> core. It is >> the bare minimum required to get Cortex-A core running with a >> semihosting >> - interface. For M-profile we only define a hardfault handler, >> required to >> - prevent the simulator from entering into an infinite loop. The >> comments >> - below apply to A-profile only. >> + interface. For M-profile we define a hardfault handler, required to >> + prevent the simulator from entering into an infinite loop and we >> enable >> + the FPU when __ARM_FP is set. >> + The comments below apply to A-profile only. > > Isn't this comment part of your other patch series? The other patch adds the hardfault handler. This patch adds the code to enable the PFU, so it updates the comment accordingly. > >> It sets up a basic 1:1 phsyical address to virtual address mapping; >> turns the MMU on; enables branch prediction; activates any >> integrated >> @@ -542,6 +543,27 @@ page_tables: >> PT7(0x1c0e) >> #elif (__ARM_ARCH_PROFILE == 'M') >> + .syntax unified >> + .thumb >> + >> + @ CPU Initialisation >> + .globl _rdimon_hw_init_hook >> + .type _rdimon_hw_init_hook, %function >> + >> +_rdimon_hw_init_hook: >> + /* Enable FPU for M-profile only . */ >> +#if __ARM_FP >> + /* Read CPACR */ >> + ldr r0, =0xE000ED88 >> + ldr r1, [R0] >> + /* Enable full access to CP10 and CP11. */ >> + orr r1, r1, #(0xFF << 20) >> + str r1, [R0] >> + dsb >> + isb > > What about the NS version of this register (@0xE002ED88) when starting > in secure state? Even if we don't want to set it here, I think we > should note that in a comment and explain why. I didn't think of it.... TBH I have been using this code in a different context for a very long time, I wrote it before NS/S existed ;-) So keep the above code unchanged and add something like #if __ARM_ARCH >= 800 ldr r0, =0xE020ED88 str r1, [R0] #endif Not sure how to test it, though. > >> +#endif >> + bx lr >> + >> /* On M-profile, call abort in case of hardfault: this causes >> the simulator to >> abort execution instead of going into an infinite loop. */ >> .section .hardfault_handler_addr, "a" >> diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S >> index b9e768007..d355405e3 100644 >> --- a/libgloss/arm/crt0.S >> +++ b/libgloss/arm/crt0.S >> @@ -253,9 +253,9 @@ >> /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however >> __ARM_ARCH_7A >> has been defined since 4.2 onwards, which is when v7-a support >> was added >> and hence 'A' profile support was added in the compiler. Allow >> for this >> - file to be built with older compilers. We only call this for A >> profile >> + file to be built with older compilers. We only call this for A >> and M profile >> cores. */ >> -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') >> +#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') || >> (__ARM_ARCH_PROFILE == 'M') > > We should include arm-acle-compat.h and drop the __ARM_ARCH_7A__ test now. Ack Thanks, Christophe > >> /* The init hook does not use the stack and is called before the >> stack has been set up. */ >> #ifdef ARM_RDI_MONITOR >> bl _rdimon_hw_init_hook > > R.
I have sent an updated version as part of a new series (now 3 patches): https://sourceware.org/pipermail/newlib/2026/022515.html On 6/22/26 15:40, Christophe Lyon wrote: > > > On 6/22/26 13:08, Richard Earnshaw wrote: >> On 19/06/2026 14:04, Christophe Lyon wrote: >>> Before using the FPU, we must grant access to it. This helps when >>> running the GCC testsuite on a simluator where FPU access is not >>> granted by default. >>> >>> This patch grants full access, we may want to consider granting only >>> unpriviledged access later. >>> >>> 2026-05-29 Christophe Lyon <christophe.lyon@arm.com> >>> >>> * libgloss/arm/cpu-init/rdimon-aem.S: Enable full FPU access on >>> M-profile. >>> * libgloss/arm/crt0.S: Call _rdimon_hw_init_hook for M profile >>> too. >>> --- >>> libgloss/arm/cpu-init/rdimon-aem.S | 28 +++++++++++++++++++++++++--- >>> libgloss/arm/crt0.S | 4 ++-- >>> 2 files changed, 27 insertions(+), 5 deletions(-) >>> >>> diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu- >>> init/rdimon-aem.S >>> index c960924d4..c8640632a 100644 >>> --- a/libgloss/arm/cpu-init/rdimon-aem.S >>> +++ b/libgloss/arm/cpu-init/rdimon-aem.S >>> @@ -25,9 +25,10 @@ >>> /* This file gives a basic initialisation of a Cortex-A series >>> core. It is >>> the bare minimum required to get Cortex-A core running with a >>> semihosting >>> - interface. For M-profile we only define a hardfault handler, >>> required to >>> - prevent the simulator from entering into an infinite loop. The >>> comments >>> - below apply to A-profile only. >>> + interface. For M-profile we define a hardfault handler, required to >>> + prevent the simulator from entering into an infinite loop and we >>> enable >>> + the FPU when __ARM_FP is set. >>> + The comments below apply to A-profile only. >> >> Isn't this comment part of your other patch series? > > The other patch adds the hardfault handler. This patch adds the code to > enable the PFU, so it updates the comment accordingly. > >> >>> It sets up a basic 1:1 phsyical address to virtual address mapping; >>> turns the MMU on; enables branch prediction; activates any >>> integrated >>> @@ -542,6 +543,27 @@ page_tables: >>> PT7(0x1c0e) >>> #elif (__ARM_ARCH_PROFILE == 'M') >>> + .syntax unified >>> + .thumb >>> + >>> + @ CPU Initialisation >>> + .globl _rdimon_hw_init_hook >>> + .type _rdimon_hw_init_hook, %function >>> + >>> +_rdimon_hw_init_hook: >>> + /* Enable FPU for M-profile only . */ >>> +#if __ARM_FP >>> + /* Read CPACR */ >>> + ldr r0, =0xE000ED88 >>> + ldr r1, [R0] >>> + /* Enable full access to CP10 and CP11. */ >>> + orr r1, r1, #(0xFF << 20) >>> + str r1, [R0] >>> + dsb >>> + isb >> >> What about the NS version of this register (@0xE002ED88) when starting >> in secure state? Even if we don't want to set it here, I think we >> should note that in a comment and explain why. > > I didn't think of it.... TBH I have been using this code in a different > context for a very long time, I wrote it before NS/S existed ;-) > > So keep the above code unchanged and add something like > #if __ARM_ARCH >= 800 > ldr r0, =0xE020ED88 > str r1, [R0] > #endif > > Not sure how to test it, though. > >> >>> +#endif >>> + bx lr >>> + >>> /* On M-profile, call abort in case of hardfault: this causes >>> the simulator to >>> abort execution instead of going into an infinite loop. */ >>> .section .hardfault_handler_addr, "a" >>> diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S >>> index b9e768007..d355405e3 100644 >>> --- a/libgloss/arm/crt0.S >>> +++ b/libgloss/arm/crt0.S >>> @@ -253,9 +253,9 @@ >>> /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however >>> __ARM_ARCH_7A >>> has been defined since 4.2 onwards, which is when v7-a support >>> was added >>> and hence 'A' profile support was added in the compiler. Allow >>> for this >>> - file to be built with older compilers. We only call this for A >>> profile >>> + file to be built with older compilers. We only call this for A >>> and M profile >>> cores. */ >>> -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') >>> +#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') || >>> (__ARM_ARCH_PROFILE == 'M') >> >> We should include arm-acle-compat.h and drop the __ARM_ARCH_7A__ test >> now. > > Ack > > Thanks, > > Christophe > >> >>> /* The init hook does not use the stack and is called before the >>> stack has been set up. */ >>> #ifdef ARM_RDI_MONITOR >>> bl _rdimon_hw_init_hook >> >> R. >
diff --git a/libgloss/arm/cpu-init/rdimon-aem.S b/libgloss/arm/cpu-init/rdimon-aem.S index c960924d4..c8640632a 100644 --- a/libgloss/arm/cpu-init/rdimon-aem.S +++ b/libgloss/arm/cpu-init/rdimon-aem.S @@ -25,9 +25,10 @@ /* This file gives a basic initialisation of a Cortex-A series core. It is the bare minimum required to get Cortex-A core running with a semihosting - interface. For M-profile we only define a hardfault handler, required to - prevent the simulator from entering into an infinite loop. The comments - below apply to A-profile only. + interface. For M-profile we define a hardfault handler, required to + prevent the simulator from entering into an infinite loop and we enable + the FPU when __ARM_FP is set. + The comments below apply to A-profile only. It sets up a basic 1:1 phsyical address to virtual address mapping; turns the MMU on; enables branch prediction; activates any integrated @@ -542,6 +543,27 @@ page_tables: PT7(0x1c0e) #elif (__ARM_ARCH_PROFILE == 'M') + .syntax unified + .thumb + + @ CPU Initialisation + .globl _rdimon_hw_init_hook + .type _rdimon_hw_init_hook, %function + +_rdimon_hw_init_hook: + /* Enable FPU for M-profile only . */ +#if __ARM_FP + /* Read CPACR */ + ldr r0, =0xE000ED88 + ldr r1, [R0] + /* Enable full access to CP10 and CP11. */ + orr r1, r1, #(0xFF << 20) + str r1, [R0] + dsb + isb +#endif + bx lr + /* On M-profile, call abort in case of hardfault: this causes the simulator to abort execution instead of going into an infinite loop. */ .section .hardfault_handler_addr, "a" diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S index b9e768007..d355405e3 100644 --- a/libgloss/arm/crt0.S +++ b/libgloss/arm/crt0.S @@ -253,9 +253,9 @@ /* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A has been defined since 4.2 onwards, which is when v7-a support was added and hence 'A' profile support was added in the compiler. Allow for this - file to be built with older compilers. We only call this for A profile + file to be built with older compilers. We only call this for A and M profile cores. */ -#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') +#if defined (__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A') || (__ARM_ARCH_PROFILE == 'M') /* The init hook does not use the stack and is called before the stack has been set up. */ #ifdef ARM_RDI_MONITOR bl _rdimon_hw_init_hook