diff mbox series

[11/12] RISC-V: strcmp() size optimized version: Use compressed registers

Message ID 20250409064701.3435-12-marlene.fally@gmail.com
State New
Headers
Series newlib: RISC-V: Optimize memory and string functions for code size |

Commit Message

m fally April 9, 2025, 6:47 a.m. UTC 
  From: puranikvinit <kvp933.vinit@gmail.com>

Swap uncompressed registers with compressed registers. Move the
li instruction downwards, so t2 can be replaced with a5.

Reviewed-by: Christian Herber <christian.herber@oss.nxp.com>
Signed-off-by: puranikvinit <kvp933.vinit@gmail.com>
---
 newlib/libc/machine/riscv/strcmp.S | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

Comments

Kito Cheng April 9, 2025, 7:18 a.m. UTC | #1 
That's the optimized for performance path, so I would prefer to keep
the li there, otherwise we will increase 5/3 instruction count per
loop on RV32/RV64.


On Wed, Apr 9, 2025 at 2:54 PM m fally <marlene.fally@gmail.com> wrote:
>
> From: puranikvinit <kvp933.vinit@gmail.com>
>
> Swap uncompressed registers with compressed registers. Move the
> li instruction downwards, so t2 can be replaced with a5.
>
> Reviewed-by: Christian Herber <christian.herber@oss.nxp.com>
> Signed-off-by: puranikvinit <kvp933.vinit@gmail.com>
> ---
>  newlib/libc/machine/riscv/strcmp.S | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/newlib/libc/machine/riscv/strcmp.S b/newlib/libc/machine/riscv/strcmp.S
> index cc29b7b8b..b49569db5 100644
> --- a/newlib/libc/machine/riscv/strcmp.S
> +++ b/newlib/libc/machine/riscv/strcmp.S
> @@ -30,8 +30,6 @@ strcmp:
>
>  .size  strcmp, .-strcmp
>  #else
> -  li    t2, -1
> -
>  #if !(__riscv_misaligned_slow || __riscv_misaligned_fast)
>    or    a4, a0, a1
>    and   a4, a4, SZREG-1
> @@ -48,12 +46,13 @@ strcmp:
>      REG_L a2, \i*SZREG(a0)
>      REG_L a3, \i*SZREG(a1)
>
> -    and   t0, a2, a5
> -    or    t1, a2, a5
> -    add   t0, t0, a5
> -    or    t0, t0, t1
> +    and   a4, a2, a5
> +    or    t0, a2, a5
> +    add   a4, a4, a5
> +    or    a4, a4, t0
>
> -    bne   t0, t2, .Lnull\i
> +    li    a5, -1
> +    bne   a4, a5, .Lnull\i
>      .if \i+1-\n
>        bne   a2, a3, .Lmismatch
>      .else
> --
> 2.49.0
>
diff mbox series

Patch

diff --git a/newlib/libc/machine/riscv/strcmp.S b/newlib/libc/machine/riscv/strcmp.S
index cc29b7b8b..b49569db5 100644
--- a/newlib/libc/machine/riscv/strcmp.S
+++ b/newlib/libc/machine/riscv/strcmp.S
@@ -30,8 +30,6 @@  strcmp:
 
 .size	strcmp, .-strcmp
 #else
-  li    t2, -1
-
 #if !(__riscv_misaligned_slow || __riscv_misaligned_fast)
   or    a4, a0, a1
   and   a4, a4, SZREG-1
@@ -48,12 +46,13 @@  strcmp:
     REG_L a2, \i*SZREG(a0)
     REG_L a3, \i*SZREG(a1)
 
-    and   t0, a2, a5
-    or    t1, a2, a5
-    add   t0, t0, a5
-    or    t0, t0, t1
+    and   a4, a2, a5
+    or    t0, a2, a5
+    add   a4, a4, a5
+    or    a4, a4, t0
 
-    bne   t0, t2, .Lnull\i
+    li    a5, -1
+    bne   a4, a5, .Lnull\i
     .if \i+1-\n
       bne   a2, a3, .Lmismatch
     .else