Message ID | 20231012100602.48059-1-sebastian.huber@embedded-brains.de |
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State | New |
Headers |
Return-Path: <newlib-bounces+patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4AE8A3858C30 for <patchwork@sourceware.org>; Thu, 12 Oct 2023 10:06:20 +0000 (GMT) X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from dedi548.your-server.de (dedi548.your-server.de [85.10.215.148]) by sourceware.org (Postfix) with ESMTPS id 66FA33858CDB for <newlib@sourceware.org>; Thu, 12 Oct 2023 10:06:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 66FA33858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embedded-brains.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embedded-brains.de Received: from sslproxy06.your-server.de ([78.46.172.3]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from <sebastian.huber@embedded-brains.de>) id 1qqsZy-0003Ax-2Y; Thu, 12 Oct 2023 12:06:06 +0200 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy06.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from <sebastian.huber@embedded-brains.de>) id 1qqsZx-000BT7-Uk; Thu, 12 Oct 2023 12:06:05 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 7D61648016B; Thu, 12 Oct 2023 12:06:05 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10032) with ESMTP id PFgdKN7qTZjT; Thu, 12 Oct 2023 12:06:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 3187D4801C2; Thu, 12 Oct 2023 12:06:05 +0200 (CEST) X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id 8HhToK45f4oF; Thu, 12 Oct 2023 12:06:05 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [192.168.96.242]) by mail.embedded-brains.de (Postfix) with ESMTPSA id D894E48016B; Thu, 12 Oct 2023 12:06:04 +0200 (CEST) From: Sebastian Huber <sebastian.huber@embedded-brains.de> To: newlib@sourceware.org Cc: Jesse Huang <jesse.huang@sifive.com>, Kito Cheng <kito.cheng@sifive.com> Subject: [PATCH] riscv: Fix fenv.h support Date: Thu, 12 Oct 2023 12:06:02 +0200 Message-Id: <20231012100602.48059-1-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authenticated-Sender: smtp-embedded@poldi-networks.de X-Virus-Scanned: Clear (ClamAV 0.103.10/27059/Thu Oct 12 09:41:08 2023) X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list <newlib.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/newlib>, <mailto:newlib-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/newlib/> List-Post: <mailto:newlib@sourceware.org> List-Help: <mailto:newlib-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/newlib>, <mailto:newlib-request@sourceware.org?subject=subscribe> Errors-To: newlib-bounces+patchwork=sourceware.org@sourceware.org |
Series |
riscv: Fix fenv.h support
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Commit Message
Sebastian Huber
Oct. 12, 2023, 10:06 a.m. UTC
Use the same C preprocessor expressions to define FE_RMODE_MASK and __RISCV_HARD_FLOAT. The problem was noticed on GCC 10 which does not define __riscv_f. --- newlib/libc/machine/riscv/sys/fenv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Comments
LGTM, I didn't notice that backwards compatible issue, thanks for fixing that :) Sebastian Huber <sebastian.huber@embedded-brains.de> 於 2023年10月12日 週四 03:06 寫道: > Use the same C preprocessor expressions to define FE_RMODE_MASK and > __RISCV_HARD_FLOAT. > > The problem was noticed on GCC 10 which does not define __riscv_f. > --- > newlib/libc/machine/riscv/sys/fenv.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/newlib/libc/machine/riscv/sys/fenv.h > b/newlib/libc/machine/riscv/sys/fenv.h > index 1d577d527b..98387d2205 100644 > --- a/newlib/libc/machine/riscv/sys/fenv.h > +++ b/newlib/libc/machine/riscv/sys/fenv.h > @@ -14,7 +14,7 @@ > > #include <stddef.h> > > -#if defined(__riscv_f) || defined(__riscv_zfinx) > +#if defined(__riscv_flen) || defined(__riscv_zfinx) > > /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: > * Version 2.1", Section 8.2, "Floating-Point Control and Status > -- > 2.35.3 > >
Feel free to merge. The file already mentions __riscv_flen in the #else clause. -- Jeff J. On Thu, Oct 12, 2023 at 6:06 AM Sebastian Huber < sebastian.huber@embedded-brains.de> wrote: > Use the same C preprocessor expressions to define FE_RMODE_MASK and > __RISCV_HARD_FLOAT. > > The problem was noticed on GCC 10 which does not define __riscv_f. > --- > newlib/libc/machine/riscv/sys/fenv.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/newlib/libc/machine/riscv/sys/fenv.h > b/newlib/libc/machine/riscv/sys/fenv.h > index 1d577d527b..98387d2205 100644 > --- a/newlib/libc/machine/riscv/sys/fenv.h > +++ b/newlib/libc/machine/riscv/sys/fenv.h > @@ -14,7 +14,7 @@ > > #include <stddef.h> > > -#if defined(__riscv_f) || defined(__riscv_zfinx) > +#if defined(__riscv_flen) || defined(__riscv_zfinx) > > /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: > * Version 2.1", Section 8.2, "Floating-Point Control and Status > -- > 2.35.3 > >
diff --git a/newlib/libc/machine/riscv/sys/fenv.h b/newlib/libc/machine/riscv/sys/fenv.h index 1d577d527b..98387d2205 100644 --- a/newlib/libc/machine/riscv/sys/fenv.h +++ b/newlib/libc/machine/riscv/sys/fenv.h @@ -14,7 +14,7 @@ #include <stddef.h> -#if defined(__riscv_f) || defined(__riscv_zfinx) +#if defined(__riscv_flen) || defined(__riscv_zfinx) /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: * Version 2.1", Section 8.2, "Floating-Point Control and Status