@@ -32,6 +32,7 @@
#:use-module (gnu packages libffi)
#:use-module (gnu packages zip)
#:use-module (gnu packages perl)
+ #:use-module (gnu packages ghostscript)
#:use-module (gnu packages gawk))
;; To compile as C code (default): make sure that CC=gcc and ABC_NAMESPACE is not defined.
@@ -54,7 +55,6 @@
`(("readline" ,readline)))
(arguments
`(#:tests? #f ; 'check target does not exist.
- ; #:make-flags '("PROG=abc")
#:phases
(modify-phases %standard-phases
(delete 'configure)
@@ -70,3 +70,29 @@
(description "ABC is a program for sequential logic synthesis and formal verification.")
(license license:expat) #| FIXME license: MIT Modern variant as described
in <https://fedoraproject.org/wiki/Licensing:MIT> |#))
+
+;; Note: compare geda.
+(define-public iverilog
+ (package
+ (name "iverilog")
+ (version "10.1.1")
+ (source (origin
+ (method url-fetch)
+ (uri
+ (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/verilog-" version ".tar.gz"))
+ (sha256
+ (base32
+ "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx"))))
+ (build-system gnu-build-system)
+ (native-inputs
+ `(("flex" ,flex)
+ ("bison" ,bison)
+ ("ghostscript" ,ghostscript) #| ps2pdf |#))
+ (home-page "http://iverilog.icarus.com/")
+ (synopsis "FPGA Verilog Simulation and Synthesis Tool")
+ (description "Icarus Verilog is a Verilog simulation and synthesis tool.
+It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
+For batch simulation, the compiler can generate an intermediate form called vvp assembly.
+This intermediate form is executed by the ``vvp'' command.
+For synthesis, the compiler generates netlists in the desired format.")
+ (license license:gpl2)))