diff mbox series

[v2] Update RISC-V relocations

Message ID mvmmspt7i9q.fsf@suse.de (mailing list archive)
State Superseded
Delegated to: Maxim Kuvyrkov
Headers
Series [v2] Update RISC-V relocations |

Checks

Context Check Description
redhat-pt-bot/TryBot-apply_patch success Patch applied to master at the time it was sent
redhat-pt-bot/TryBot-32bit success Build for i686
linaro-tcwg-bot/tcwg_glibc_build--master-arm success Testing passed
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linaro-tcwg-bot/tcwg_glibc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_glibc_check--master-aarch64 success Testing passed

Commit Message

Andreas Schwab April 16, 2024, 9:45 a.m. UTC 
  This updates the list of RISC-V relocations from the ELF psABI as of Apr
2024.  It removes binutils-internal only relocations that were never part
of actual object files.  The GNU_VTINHERIT and GNU_VTENTRY relocations
were never used because the corresponding GCC option -fvtable-gc was never
supported on RISC-V.
---
v2: Remove GPREL relocations.  They were recently removed again from the
ABI, as they are only supposed to be linker-internal.
---
 elf/elf.h | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/elf/elf.h b/elf/elf.h
index 55b2e87860..6a4e1d7512 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -4080,6 +4080,7 @@  enum
 #define R_RISCV_TLS_DTPREL64	 9
 #define R_RISCV_TLS_TPREL32	10
 #define R_RISCV_TLS_TPREL64	11
+#define R_RISCV_TLSDESC		12
 #define R_RISCV_BRANCH		16
 #define R_RISCV_JAL		17
 #define R_RISCV_CALL		18
@@ -4105,16 +4106,10 @@  enum
 #define R_RISCV_SUB16		38
 #define R_RISCV_SUB32		39
 #define R_RISCV_SUB64		40
-#define R_RISCV_GNU_VTINHERIT	41
-#define R_RISCV_GNU_VTENTRY	42
+#define R_RISCV_GOT32_PCREL	41
 #define R_RISCV_ALIGN		43
 #define R_RISCV_RVC_BRANCH	44
 #define R_RISCV_RVC_JUMP	45
-#define R_RISCV_RVC_LUI		46
-#define R_RISCV_GPREL_I		47
-#define R_RISCV_GPREL_S		48
-#define R_RISCV_TPREL_I		49
-#define R_RISCV_TPREL_S		50
 #define R_RISCV_RELAX		51
 #define R_RISCV_SUB6		52
 #define R_RISCV_SET6		53
@@ -4126,8 +4121,12 @@  enum
 #define R_RISCV_PLT32		59
 #define R_RISCV_SET_ULEB128	60
 #define R_RISCV_SUB_ULEB128	61
+#define R_RISCV_TLSDESC_HI20	62
+#define R_RISCV_TLSDESC_LOAD_LO12 63
+#define R_RISCV_TLSDESC_ADD_LO12 64
+#define R_RISCV_TLSDESC_CALL	65
 
-#define R_RISCV_NUM		62
+#define R_RISCV_NUM		66
 
 /* RISC-V specific values for the st_other field.  */
 #define STO_RISCV_VARIANT_CC	0x80	/* Function uses variant calling