Add NT_ARM_GCS and NT_RISCV_TAGGED_ADDR_CTRL from Linux 6.13 to elf.h
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Commit Message
Linux 6.13 adds new ELF note types NT_ARM_GCS and
NT_RISCV_TAGGED_ADDR_CTRL. Add these to glibc's elf.h.
Tested for x86_64.
Comments
On 09/04/25 17:55, Joseph Myers wrote:
> Linux 6.13 adds new ELF note types NT_ARM_GCS and
> NT_RISCV_TAGGED_ADDR_CTRL. Add these to glibc's elf.h.
>
> Tested for x86_64.
LGTM, thanks.
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
>
> diff --git a/elf/elf.h b/elf/elf.h
> index c0f61489ec..1e1a59c14d 100644
> --- a/elf/elf.h
> +++ b/elf/elf.h
> @@ -837,12 +837,15 @@ typedef struct
> #define NT_ARM_ZT 0x40d /* ARM SME ZT registers. */
> #define NT_ARM_FPMR 0x40e /* ARM floating point mode register. */
> #define NT_ARM_POE 0x40f /* ARM POE registers. */
> +#define NT_ARM_GCS 0x410 /* ARM GCS state. */
> #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note. */
> #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers. */
> #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode. */
> #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers. */
> #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
> #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
> +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged
> + address control */
> #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */
> #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and
> status registers. */
>
@@ -837,12 +837,15 @@ typedef struct
#define NT_ARM_ZT 0x40d /* ARM SME ZT registers. */
#define NT_ARM_FPMR 0x40e /* ARM floating point mode register. */
#define NT_ARM_POE 0x40f /* ARM POE registers. */
+#define NT_ARM_GCS 0x410 /* ARM GCS state. */
#define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note. */
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers. */
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode. */
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers. */
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
+#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged
+ address control */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers. */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and
status registers. */