[v5,05/17] RISC-V: Support dynamic loader for the 32-bit

From: Zong Li <zongbox@gmail.com>

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WDCIronportException: Internal
To: libc-alpha@sourceware.org
Subject: [PATCH v5 05/17] RISC-V: Support dynamic loader for the 32-bit
Date: Wed, 19 Aug 2020 08:38:51 -0700
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 <e7ed7db367ce8540f65acea8281984d6b397cd47.1597851293.git.alistair.francis@wdc.com>
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Message ID	e7ed7db367ce8540f65acea8281984d6b397cd47.1597851293.git.alistair.francis@wdc.com
State	Committed
Headers	DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 04E1A386F810 IronPort-SDR: 85gYUKSDKn2cBxI8Hr/5+im1OiSGNVScfLwQw6nXxzsFtjCY5TZPjYlXLfQjhUeJj2GXcALbvE xQW9ZS5KrD9MfGTTF/196j0R0Img90IK0CsojcK6a9dAVI7JcJUOxLJTl7sg+uIdRWFSmHlhaw 4BK6O/qdkeXR10+dSTlgZXY5dWZ8FK9SqPXpxuAvzQJQ14gtHUE70wx4rlTHqCZpj1TANbrNo/ xnEHzvWoQ77cPbb/outvMS29XtoLuFa5cJhFidwy0KkxLQ3EG1nb6E9tXZDx4y8tNZTZPmX/p2 BOU= IronPort-SDR: UImp6xEdrNb2YEZ9vdl1R66Z0EN4fkvUJKXUA5qNUKUyrZbYjsS/MYe5IhIP88ng9HOoe0qMOY 7HJ+n0zXP3hA== IronPort-SDR: cMc/oXC99P7z8/BF6mBGrrWeusGH7mrmzTVFcSrxkQe9lJ/zTe+30DVifidFtGK7HWwH4EOtFN /L4va/TWx1Qw== WDCIronportException: Internal To: libc-alpha@sourceware.org Subject: [PATCH v5 05/17] RISC-V: Support dynamic loader for the 32-bit Date: Wed, 19 Aug 2020 08:38:51 -0700 Message-Id: <e7ed7db367ce8540f65acea8281984d6b397cd47.1597851293.git.alistair.francis@wdc.com> In-Reply-To: <cover.1597851293.git.alistair.francis@wdc.com> References: <cover.1597851293.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: Alistair Francis via Libc-alpha <libc-alpha@sourceware.org> Reply-To: Alistair Francis <alistair.francis@wdc.com> Cc: alistair.francis@wdc.com Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces@sourceware.org>
Series	glibc port for 32-bit RISC-V (RV32) \| [v5,00/17] glibc port for 32-bit RISC-V (RV32) [v5,01/17] RISC-V: Use 64-bit time_t and off_t for RV32 and RV64 [v5,02/17] RISC-V: Cleanup some of the sysdep.h code [v5,03/17] RISC-V: Use 64-bit-time syscall numbers with the 32-bit port [v5,04/17] RISC-V: Add support for 32-bit vDSO calls [v5,05/17] RISC-V: Support dynamic loader for the 32-bit [v5,06/17] RISC-V: Add path of library directories for the 32-bit [v5,07/17] RISC-V: Add arch-syscall.h for RV32 [v5,08/17] RISC-V: Support the 32-bit ABI implementation [v5,09/17] RISC-V: Add hard float support for 32-bit CPUs [v5,10/17] RISC-V: Add 32-bit ABI lists [v5,11/17] RISC-V: Add the RV32 libm-test-ulps [v5,12/17] RISC-V: Fix llrint and llround missing exceptions on RV32 [v5,13/17] riscv32: Specify the arch_minimum_kernel as 5.4 [v5,14/17] RISC-V: Add rv32 path to RTLDLIST in ldd [v5,15/17] RISC-V: Build infastructure for 32-bit port [v5,16/17] Documentation for the RISC-V 32-bit port [v5,17/17] Add RISC-V 32-bit target to build-many-glibcs.py

[v5,05/17] RISC-V: Support dynamic loader for the 32-bit

Commit Message

Patch