diff mbox

[MIPS] Modify __mpn routines for mips32r6/mips64r6

Message ID bb9daa48-0742-4bae-b5f8-7f5f0a23f9ae@BAMAIL02.ba.imgtec.org
State Committed
Headers

Commit Message

Steve Ellcey Dec. 19, 2014, 9:29 p.m. UTC 
  Support for mips32r6 and mips64r6 has been checked into GCC and binutils
and there are a few changes needed for glibc as well.  Here is the first
of the patches, it replaces the use of multu with mulu/muhu in the __mpn
multi-precision math routines.  multu, which put the results in the high
and low registers is not supported in mip32r6 and mips64r6 and has been
replaced by mulu/muhu which put the high and low results into registers
specified in the instruction.

Tested with the mips32r6/mips64r6 GCC, binutils and qemu simulator.

OK to checkin?

Steve Ellcey
sellcey@imgtec.com


2014-12-19  Steve Ellcey  <sellcey@imgtec.com>

	* sysdeps/mips/addmul_1.S (__mpn_addmul_1): Use mulu/muhu instead
	of multu on MIPSr6.
	* sysdeps/mips/mul_1.S (__mpn_mul_1): Ditto.
	* sysdeps/mips/submul_1.S (__mpn_submul_1): Ditto.
	* sysdeps/mips/mips64/addmul_1.S (__mpn_addmul_1): Ditto.
	* sysdeps/mips/mips64/mul_1.S (__mpn_mul_1): Ditto.
	* sysdeps/mips/mips64/submul_1.S (__mpn_submul_1): Ditto.

Comments

Joseph Myers Dec. 19, 2014, 9:49 p.m. UTC | #1 
On Fri, 19 Dec 2014, Steve Ellcey  wrote:

> Support for mips32r6 and mips64r6 has been checked into GCC and binutils
> and there are a few changes needed for glibc as well.  Here is the first
> of the patches, it replaces the use of multu with mulu/muhu in the __mpn
> multi-precision math routines.  multu, which put the results in the high
> and low registers is not supported in mip32r6 and mips64r6 and has been
> replaced by mulu/muhu which put the high and low results into registers
> specified in the instruction.
> 
> Tested with the mips32r6/mips64r6 GCC, binutils and qemu simulator.
> 
> OK to checkin?

OK.  If the same code is present in current GMP (more generally, if GMP 
has MIPS assembler code affected by this issue) you'll want to submit the 
patch there as well.
diff mbox

Patch

diff --git a/sysdeps/mips/addmul_1.S b/sysdeps/mips/addmul_1.S
index 2c4c34b..084080e 100644
--- a/sysdeps/mips/addmul_1.S
+++ b/sysdeps/mips/addmul_1.S
@@ -42,7 +42,12 @@  ENTRY (__mpn_addmul_1)
 
 	/* warm up phase 1 */
 	addiu	$5,$5,4
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 
 	addiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -53,11 +58,21 @@  ENTRY (__mpn_addmul_1)
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 
 L(Loop):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addiu	$5,$5,4
 	addu	$3,$3,$2	/* add old carry limb to low product limb */
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 	addiu	$6,$6,-1	/* decrement loop counter */
 	sltu	$2,$3,$2	/* carry from previous addition -> $2 */
@@ -71,11 +86,21 @@  L(Loop):	lw	$10,0($4)
 
 	/* cool down phase 1 */
 L(LC1):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	addu	$3,$10,$3
 	sltu	$10,$3,$10
 	addu	$2,$2,$10
@@ -85,8 +110,13 @@  L(LC1):	lw	$10,0($4)
 
 	/* cool down phase 0 */
 L(LC0):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
 	addu	$3,$10,$3
diff --git a/sysdeps/mips/mips64/addmul_1.S b/sysdeps/mips/mips64/addmul_1.S
index 57edd4a..4f035f9 100644
--- a/sysdeps/mips/mips64/addmul_1.S
+++ b/sysdeps/mips/mips64/addmul_1.S
@@ -44,7 +44,12 @@  ENTRY (__mpn_addmul_1)
 
  # warm up phase 1
 	daddiu	$5,$5,8
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 
 	daddiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -55,11 +60,21 @@  ENTRY (__mpn_addmul_1)
 	ld	$8,0($5)	# load new s1 limb as early as possible
 
 L(Loop):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddiu	$5,$5,8
 	daddu	$3,$3,$2	# add old carry limb to low product limb
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	ld	$8,0($5)	# load new s1 limb as early as possible
 	daddiu	$6,$6,-1	# decrement loop counter
 	sltu	$2,$3,$2	# carry from previous addition -> $2
@@ -73,11 +88,21 @@  L(Loop):	ld	$10,0($4)
 
  # cool down phase 1
 L(LC1):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	daddu	$3,$10,$3
 	sltu	$10,$3,$10
 	daddu	$2,$2,$10
@@ -87,8 +112,13 @@  L(LC1):	ld	$10,0($4)
 
  # cool down phase 0
 L(LC0):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
 	daddu	$3,$10,$3
diff --git a/sysdeps/mips/mips64/mul_1.S b/sysdeps/mips/mips64/mul_1.S
index a8d8078..0e5b734 100644
--- a/sysdeps/mips/mips64/mul_1.S
+++ b/sysdeps/mips/mips64/mul_1.S
@@ -45,7 +45,12 @@  ENTRY (__mpn_mul_1)
 
  # warm up phase 1
 	daddiu	$5,$5,8
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 
 	daddiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -55,11 +60,21 @@  ENTRY (__mpn_mul_1)
 	beq	$6,$0,L(LC1)
 	ld	$8,0($5)	# load new s1 limb as early as possible
 
+#if __mips_isa_rev < 6
 L(Loop):	mflo	$10
 	mfhi	$9
+#else
+L(Loop):	move	$10,$11
+		move	$9,$12
+#endif
 	daddiu	$5,$5,8
 	daddu	$10,$10,$2	# add old carry limb to low product limb
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	ld	$8,0($5)	# load new s1 limb as early as possible
 	daddiu	$6,$6,-1	# decrement loop counter
 	sltu	$2,$10,$2	# carry from previous addition -> $2
@@ -69,18 +84,33 @@  L(Loop):	mflo	$10
 	daddu	$2,$9,$2	# add high product limb and carry from addition
 
  # cool down phase 1
+#if __mips_isa_rev < 6
 L(LC1):	mflo	$10
 	mfhi	$9
+#else
+L(LC1):	move	$10,$11
+	move	$9,$12
+#endif
 	daddu	$10,$10,$2
 	sltu	$2,$10,$2
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	sd	$10,0($4)
 	daddiu	$4,$4,8
 	daddu	$2,$9,$2	# add high product limb and carry from addition
 
  # cool down phase 0
+#if  __mips_isa_rev < 6
 L(LC0):	mflo	$10
 	mfhi	$9
+#else
+L(LC0):	move	$10,$11
+	move	$9,$12
+#endif
 	daddu	$10,$10,$2
 	sltu	$2,$10,$2
 	sd	$10,0($4)
diff --git a/sysdeps/mips/mips64/submul_1.S b/sysdeps/mips/mips64/submul_1.S
index bf24123..84e9a91 100644
--- a/sysdeps/mips/mips64/submul_1.S
+++ b/sysdeps/mips/mips64/submul_1.S
@@ -45,7 +45,12 @@  ENTRY (__mpn_submul_1)
 
  # warm up phase 1
 	daddiu	$5,$5,8
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 
 	daddiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -56,11 +61,21 @@  ENTRY (__mpn_submul_1)
 	ld	$8,0($5)	# load new s1 limb as early as possible
 
 L(Loop):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddiu	$5,$5,8
 	daddu	$3,$3,$2	# add old carry limb to low product limb
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	ld	$8,0($5)	# load new s1 limb as early as possible
 	daddiu	$6,$6,-1	# decrement loop counter
 	sltu	$2,$3,$2	# carry from previous addition -> $2
@@ -74,11 +89,21 @@  L(Loop):	ld	$10,0($4)
 
  # cool down phase 1
 L(LC1):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
+#if __mips_isa_rev < 6
 	dmultu	$8,$7
+#else
+	dmulu	$11,$8,$7
+	dmuhu	$12,$8,$7
+#endif
 	dsubu	$3,$10,$3
 	sgtu	$10,$3,$10
 	daddu	$2,$2,$10
@@ -88,8 +113,13 @@  L(LC1):	ld	$10,0($4)
 
  # cool down phase 0
 L(LC0):	ld	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	daddu	$3,$3,$2
 	sltu	$2,$3,$2
 	dsubu	$3,$10,$3
diff --git a/sysdeps/mips/mul_1.S b/sysdeps/mips/mul_1.S
index c2db68a..c3368f3 100644
--- a/sysdeps/mips/mul_1.S
+++ b/sysdeps/mips/mul_1.S
@@ -42,7 +42,12 @@  ENTRY (__mpn_mul_1)
 
 	/* warm up phase 1 */
 	addiu	$5,$5,4
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 
 	addiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -52,11 +57,22 @@  ENTRY (__mpn_mul_1)
 	beq	$6,$0,L(LC1)
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 
+
+#if  __mips_isa_rev < 6
 L(Loop):	mflo	$10
 	mfhi	$9
+#else
+L(Loop):	move	$10,$11
+	move	$9,$12
+#endif
 	addiu	$5,$5,4
 	addu	$10,$10,$2	/* add old carry limb to low product limb */
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 	addiu	$6,$6,-1	/* decrement loop counter */
 	sltu	$2,$10,$2	/* carry from previous addition -> $2 */
@@ -66,18 +82,33 @@  L(Loop):	mflo	$10
 	addu	$2,$9,$2	/* add high product limb and carry from addition */
 
 	/* cool down phase 1 */
+#if __mips_isa_rev < 6
 L(LC1):	mflo	$10
 	mfhi	$9
+#else
+L(LC1):	move	$10,$11
+	move	$9,$12
+#endif
 	addu	$10,$10,$2
 	sltu	$2,$10,$2
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	sw	$10,0($4)
 	addiu	$4,$4,4
 	addu	$2,$9,$2	/* add high product limb and carry from addition */
 
 	/* cool down phase 0 */
+#if __mips_isa_rev < 6
 L(LC0):	mflo	$10
 	mfhi	$9
+#else
+L(LC0):	move	$10,$11
+	move	$9,$12
+#endif
 	addu	$10,$10,$2
 	sltu	$2,$10,$2
 	sw	$10,0($4)
diff --git a/sysdeps/mips/submul_1.S b/sysdeps/mips/submul_1.S
index ce888d4..4b8a265 100644
--- a/sysdeps/mips/submul_1.S
+++ b/sysdeps/mips/submul_1.S
@@ -42,7 +42,13 @@  ENTRY (__mpn_submul_1)
 
 	/* warm up phase 1 */
 	addiu	$5,$5,4
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
+	
 
 	addiu	$6,$6,-1
 	beq	$6,$0,L(LC0)
@@ -53,11 +59,21 @@  ENTRY (__mpn_submul_1)
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 
 L(Loop):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addiu	$5,$5,4
 	addu	$3,$3,$2	/* add old carry limb to low product limb */
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	lw	$8,0($5)	/* load new s1 limb as early as possible */
 	addiu	$6,$6,-1	/* decrement loop counter */
 	sltu	$2,$3,$2	/* carry from previous addition -> $2 */
@@ -71,11 +87,21 @@  L(Loop):	lw	$10,0($4)
 
 	/* cool down phase 1 */
 L(LC1):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
+#if __mips_isa_rev < 6
 	multu	$8,$7
+#else
+	mulu	$11,$8,$7
+	muhu	$12,$8,$7
+#endif
 	subu	$3,$10,$3
 	sgtu	$10,$3,$10
 	addu	$2,$2,$10
@@ -85,8 +111,13 @@  L(LC1):	lw	$10,0($4)
 
 	/* cool down phase 0 */
 L(LC0):	lw	$10,0($4)
+#if __mips_isa_rev < 6
 	mflo	$3
 	mfhi	$9
+#else
+	move	$3,$11
+	move	$9,$12
+#endif
 	addu	$3,$3,$2
 	sltu	$2,$3,$2
 	subu	$3,$10,$3