diff mbox

[02/12] Add fesetexcept: aarch64

Message ID alpine.DEB.2.20.1608112058170.1591@digraph.polyomino.org.uk
State Committed
Headers

Commit Message

Joseph Myers Aug. 11, 2016, 8:58 p.m. UTC 
  This patch adds an AArch64 version of fesetexcept.  Untested.

2016-08-11  Joseph Myers  <joseph@codesourcery.com>

	* sysdeps/aarch64/fpu/fesetexcept.c: New file.

Comments

Paul Eggert Aug. 11, 2016, 9:45 p.m. UTC | #1 
Thanks, that patch series looks good, though I have one minor question and/or 
quibble.

> +  if (fpsr != fpsr_new)
> +    _FPU_SETFPSR (fpsr_new);

I assume that the 'if (fpsr != fpsr_new)' is present purely for performance 
reasons, i.e., that the code would be correct if '_FPU_SETFPSR (fpsr_new)' were 
executed unconditionally. Are practical programs likely to see a performance 
improvement because of the 'if (fpsr != fpsr_new)'? My guess is no, because 
typically programs will use fesetexcept to change settings. If my guess is 
right, I'd omit the 'if (fpsr != fpsr_new)' test, on the grounds of simplicity.

Similarly for arm, hppa, powerpc.
Joseph Myers Aug. 11, 2016, 11:30 p.m. UTC | #2 
On Thu, 11 Aug 2016, Paul Eggert wrote:

> Thanks, that patch series looks good, though I have one minor question and/or
> quibble.
> 
> > +  if (fpsr != fpsr_new)
> > +    _FPU_SETFPSR (fpsr_new);
> 
> I assume that the 'if (fpsr != fpsr_new)' is present purely for performance
> reasons, i.e., that the code would be correct if '_FPU_SETFPSR (fpsr_new)'
> were executed unconditionally. Are practical programs likely to see a
> performance improvement because of the 'if (fpsr != fpsr_new)'? My guess is
> no, because typically programs will use fesetexcept to change settings. If my
> guess is right, I'd omit the 'if (fpsr != fpsr_new)' test, on the grounds of
> simplicity.

I'm deliberately following the fesetexceptflag implementations for each 
architecture, as the most similar C99/C11 function.  If those have this 
optimization, then I'm including it in fesetexcept as well.  Doing 
otherwise would make fesetexcept for AArch64 inconsistent with all the 
other <fenv.h> function implementations for AArch64, which systematically 
use this optimization (either directly, or in the <fenv_private.h> 
functions they call).

Similarly, when I implement fesetmode, that will have this optimization on 
architectures where fesetenv does.
diff mbox

Patch

diff --git a/sysdeps/aarch64/fpu/fesetexcept.c b/sysdeps/aarch64/fpu/fesetexcept.c
new file mode 100644
index 0000000..52210bb
--- /dev/null
+++ b/sysdeps/aarch64/fpu/fesetexcept.c
@@ -0,0 +1,34 @@ 
+/* Set given exception flags.  AArch64 version.
+   Copyright (C) 2016 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#include <fenv.h>
+#include <fpu_control.h>
+
+int
+fesetexcept (int excepts)
+{
+  fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
+
+  _FPU_GETFPSR (fpsr);
+  fpsr_new = fpsr | (excepts & FE_ALL_EXCEPT);
+  if (fpsr != fpsr_new)
+    _FPU_SETFPSR (fpsr_new);
+
+  return 0;
+}