[AArch64] Use builtins for fpcr/fpsr
Commit Message
Szabolcs Nagy wrote:
> this will have to wait for the next release, but please
> increase the gcc prereq to 6.0 because i see ice on gcc-5:
aarch64-none-linux-gnu-gcc ../sysdeps/aarch64/fpu/fesetenv.c -c [..]
../sysdeps/aarch64/fpu/fesetenv.c: In function '__fesetenv':
../sysdeps/aarch64/fpu/fesetenv.c:75:1: error: unrecognizable insn:
}
^
(insn 23 22 4 6 (unspec_volatile [
(mem:SI (plus:DI (reg/v/f:DI 85 [ envp ])
(const_int 4 [0x4])) [2 envp_8(D)->__fpsr+0 S4 A32])
] UNSPECV_SET_FPSR) ../sysdeps/aarch64/fpu/fesetenv.c:41 -1
(nil))
../sysdeps/aarch64/fpu/fesetenv.c:75:1: internal compiler error: in extract_insn, at recog.c:2343
Looks like it's merging a MEM into a register operand. Since GCC5 is no longer
supported I've updated it to GCC6:
Since GCC has support for accessing FPSR/FPCR, use them when possible
so that the asm instructions can be removed eventually. Although GCC 5
supports the builtins, it has an optimization bug, so use them from GCC 6
onwards.
GLIBC build and test OK.
ChangeLog:
2018-01-19 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/fpu/fpu_control.h: Use builtins for accessing FPCR/FPSR.
@@ -21,17 +21,24 @@
/* Macros for accessing the FPCR and FPSR. */
-#define _FPU_GETCW(fpcr) \
+#if __GNUC_PREREQ (6,0)
+# define _FPU_GETCW(fpcr) (fpcr = __builtin_aarch64_get_fpcr ())
+# define _FPU_SETCW(fpcr) __builtin_aarch64_set_fpcr (fpcr)
+# define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
+# define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
+#else
+# define _FPU_GETCW(fpcr) \
__asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr))
-#define _FPU_SETCW(fpcr) \
+# define _FPU_SETCW(fpcr) \
__asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr))
-#define _FPU_GETFPSR(fpsr) \
+# define _FPU_GETFPSR(fpsr) \
__asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr))
-#define _FPU_SETFPSR(fpsr) \
+# define _FPU_SETFPSR(fpsr) \
__asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr))
+#endif
/* Reserved bits should be preserved when modifying register
contents. These two masks indicate which bits in each of FPCR and