diff mbox series

x86: Detect APX_NCI_NDD_NF

Message ID CAMe9rOqb3ZfwDg4KB7gvC-3Zzqw8hJUFzv2trw9iQieJppjNog@mail.gmail.com (mailing list archive)
State Superseded
Delegated to: Adhemerval Zanella Netto
Headers
Series x86: Detect APX_NCI_NDD_NF |

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Commit Message

H.J. Lu Aug. 30, 2026, 11:28 p.m. UTC 
  Detect APX_NCI_NDD_NF specified in Intel APX specification published in
January 2026:

https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

Comments

Adhemerval Zanella Netto Sept. 2, 2026, 5:47 p.m. UTC | #1 
On 30/08/26 20:28, H.J. Lu wrote:
> Detect APX_NCI_NDD_NF specified in Intel APX specification published in
> January 2026:
> 
> https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
> 
> From 948bcc5b8d38aa22a100d84b20bb47bef1fb0c87 Mon Sep 17 00:00:00 2001
> From: "H.J. Lu" <hjl.tools@gmail.com>
> Date: Mon, 31 Aug 2026 07:21:12 +0800
> Subject: [PATCH] x86: Detect APX_NCI_NDD_NF
> 
> Detect APX_NCI_NDD_NF specified in Intel APX specification published in
> January 2026:
> 
> https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
> 
> Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
> ---
>  manual/platform.texi               |  5 +++++
>  sysdeps/x86/bits/platform/x86.h    |  9 ++++++++-
>  sysdeps/x86/cpu-features.c         | 15 +++++++++++++++
>  sysdeps/x86/include/cpu-features.h | 17 ++++++++++++++++-
>  sysdeps/x86/tst-get-cpu-features.c |  2 ++
>  5 files changed, 46 insertions(+), 2 deletions(-)
> 
> diff --git a/manual/platform.texi b/manual/platform.texi
> index cb89e4432d..011d3501fb 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -217,6 +217,11 @@ The supported processor features are:
>  @item
>  @code{APX_F} -- The APX instruction extensions.
>  
> +@item
> +@code{APX_NCI_NDD_NF} -- The instruction extensions with APX new
> +conditional instructions (NCI), explicit new data destination (NDD)
> +controls, and explicit flags suppression (NF).
> +
>  @item
>  @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
>  
> diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
> index c646e36b28..7b81a07465 100644
> --- a/sysdeps/x86/bits/platform/x86.h
> +++ b/sysdeps/x86/bits/platform/x86.h
> @@ -32,7 +32,8 @@ enum
>    CPUID_INDEX_19,
>    CPUID_INDEX_14_ECX_0,
>    CPUID_INDEX_24_ECX_0,
> -  CPUID_INDEX_24_ECX_1
> +  CPUID_INDEX_24_ECX_1,
> +  CPUID_INDEX_29_ECX_0
>  };
>  
>  struct cpuid_feature
> @@ -345,4 +346,10 @@ enum
>  
>    x86_cpu_AVX10_V1_AUX		= x86_cpu_index_24_ecx_1_ecx + 2,
>    x86_cpu_AVX10_V2_AUX		= x86_cpu_index_24_ecx_1_ecx + 3,
> +
> +  x86_cpu_index_29_ecx_0_ebx
> +    = (CPUID_INDEX_29_ECX_0 * 8 * 4 * sizeof (unsigned int)
> +       + cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
> +
> +  x86_cpu_APX_NCI_NDD_NF	= x86_cpu_index_29_ecx_0_ebx,
>  };
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index ecbcb3c78b..0b744f95a9 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -288,6 +288,21 @@ update_active (struct cpu_features *cpu_features)
>  	    }
>  	}
>  
> +      if (cpu_features->basic.max_cpuid >= 0x29)
> +	{
> +	  __cpuid_count
> +	    (0x29, 0,
> +	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.eax,
> +	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.ebx,
> +	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.ecx,
> +	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.edx);
> +
> +	  if (CPU_FEATURES_CPU_P (cpu_features, APX_F))
> +	    {
> +	      CPU_FEATURE_SET_ACTIVE (cpu_features, APX_NCI_NDD_NF);

This enables APX_NCI_NDD_NF when presents on cpuid, but later the code as 
disables APX_F if not supported by the kernel:

 307       /* APX is usable only if the APX state is supported by kernel.  */
 308       if ((xcrlow & bit_APX_state) != 0)
 309         CPU_FEATURE_SET_ACTIVE (cpu_features, APX_F);

I think we should disable APX_NCI_NDD_NF as well in this case. 

Maybe also devise a way multiple options to be disable if the kernel support
is not present, to prevent issues like that (so you only add the logic
to enable it once).

The rest looks ok.

> +	    }
> +	}
> +
>        /* Are XTILECFG and XTILEDATA states usable?  */
>        if ((xcrlow & (bit_XTILECFG_state | bit_XTILEDATA_state))
>  	  == (bit_XTILECFG_state | bit_XTILEDATA_state))
> diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
> index ec9076e261..bb632d8ce1 100644
> --- a/sysdeps/x86/include/cpu-features.h
> +++ b/sysdeps/x86/include/cpu-features.h
> @@ -29,7 +29,7 @@
>  
>  enum
>  {
> -  CPUID_INDEX_MAX = CPUID_INDEX_24_ECX_1 + 1
> +  CPUID_INDEX_MAX = CPUID_INDEX_29_ECX_0 + 1
>  };
>  
>  enum
> @@ -348,6 +348,11 @@ enum
>  #define bit_cpu_AVX10_V1_AUX	(1u << 2)
>  #define bit_cpu_AVX10_V2_AUX	(1u << 3)
>  
> +/* CPUID_INDEX_29_ECX_0.  */
> +
> +/* EBX.  */
> +#define bit_cpu_APX_NCI_NDD_NF	(1u << 0)
> +
>  /* CPUID_INDEX_1.  */
>  
>  /* ECX.  */
> @@ -610,6 +615,11 @@ enum
>  #define index_AVX10_V1_AUX	CPUID_INDEX_24_ECX_1
>  #define index_AVX10_V2_AUX	CPUID_INDEX_24_ECX_1
>  
> +/* CPUID_INDEX_29_ECX_0.  */
> +
> +/* EBX.  */
> +#define index_cpu_APX_NCI_NDD_NF CPUID_INDEX_29_ECX_0
> +
>  /* CPUID_INDEX_1.  */
>  
>  /* ECX.  */
> @@ -872,6 +882,11 @@ enum
>  #define reg_AVX10_V1_AUX	ecx
>  #define reg_AVX10_V2_AUX	ecx
>  
> +/* CPUID_INDEX_29_ECX_0.  */
> +
> +/* EBX.  */
> +#define reg_APX_NCI_NDD_NF	ebx
> +
>  /* PREFERRED_FEATURE_INDEX_1.  First define the bitindex values
>     sequentially, then define the bit_arch* and index_arch_* lookup
>     constants.  */
> diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
> index c6af1793fe..83c5cbc29e 100644
> --- a/sysdeps/x86/tst-get-cpu-features.c
> +++ b/sysdeps/x86/tst-get-cpu-features.c
> @@ -224,6 +224,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_PRESENT (AESKLE);
>    CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
>    CHECK_CPU_FEATURE_PRESENT (PTWRITE);
> +  CHECK_CPU_FEATURE_PRESENT (APX_NCI_NDD_NF);
>  
>    printf ("Possible CPU features:\n");
>    CHECK_CPU_FEATURE_ACTIVE (SSE3);
> @@ -397,6 +398,7 @@ do_test (void)
>    CHECK_CPU_FEATURE_ACTIVE (AESKLE);
>    CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
>    CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
> +  CHECK_CPU_FEATURE_ACTIVE (APX_NCI_NDD_NF);
>  
>    unsigned int version = x86_get_avx10_version ();
>    printf ("AVX10 version: %d\n", version);
> -- 
> 2.55.0
>
diff mbox series

Patch

From 948bcc5b8d38aa22a100d84b20bb47bef1fb0c87 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Mon, 31 Aug 2026 07:21:12 +0800
Subject: [PATCH] x86: Detect APX_NCI_NDD_NF

Detect APX_NCI_NDD_NF specified in Intel APX specification published in
January 2026:

https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
---
 manual/platform.texi               |  5 +++++
 sysdeps/x86/bits/platform/x86.h    |  9 ++++++++-
 sysdeps/x86/cpu-features.c         | 15 +++++++++++++++
 sysdeps/x86/include/cpu-features.h | 17 ++++++++++++++++-
 sysdeps/x86/tst-get-cpu-features.c |  2 ++
 5 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/manual/platform.texi b/manual/platform.texi
index cb89e4432d..011d3501fb 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -217,6 +217,11 @@  The supported processor features are:
 @item
 @code{APX_F} -- The APX instruction extensions.
 
+@item
+@code{APX_NCI_NDD_NF} -- The instruction extensions with APX new
+conditional instructions (NCI), explicit new data destination (NDD)
+controls, and explicit flags suppression (NF).
+
 @item
 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
 
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index c646e36b28..7b81a07465 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -32,7 +32,8 @@  enum
   CPUID_INDEX_19,
   CPUID_INDEX_14_ECX_0,
   CPUID_INDEX_24_ECX_0,
-  CPUID_INDEX_24_ECX_1
+  CPUID_INDEX_24_ECX_1,
+  CPUID_INDEX_29_ECX_0
 };
 
 struct cpuid_feature
@@ -345,4 +346,10 @@  enum
 
   x86_cpu_AVX10_V1_AUX		= x86_cpu_index_24_ecx_1_ecx + 2,
   x86_cpu_AVX10_V2_AUX		= x86_cpu_index_24_ecx_1_ecx + 3,
+
+  x86_cpu_index_29_ecx_0_ebx
+    = (CPUID_INDEX_29_ECX_0 * 8 * 4 * sizeof (unsigned int)
+       + cpuid_register_index_ebx * 8 * sizeof (unsigned int)),
+
+  x86_cpu_APX_NCI_NDD_NF	= x86_cpu_index_29_ecx_0_ebx,
 };
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index ecbcb3c78b..0b744f95a9 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -288,6 +288,21 @@  update_active (struct cpu_features *cpu_features)
 	    }
 	}
 
+      if (cpu_features->basic.max_cpuid >= 0x29)
+	{
+	  __cpuid_count
+	    (0x29, 0,
+	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.eax,
+	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.ebx,
+	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.ecx,
+	     cpu_features->features[CPUID_INDEX_29_ECX_0].cpuid.edx);
+
+	  if (CPU_FEATURES_CPU_P (cpu_features, APX_F))
+	    {
+	      CPU_FEATURE_SET_ACTIVE (cpu_features, APX_NCI_NDD_NF);
+	    }
+	}
+
       /* Are XTILECFG and XTILEDATA states usable?  */
       if ((xcrlow & (bit_XTILECFG_state | bit_XTILEDATA_state))
 	  == (bit_XTILECFG_state | bit_XTILEDATA_state))
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index ec9076e261..bb632d8ce1 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -29,7 +29,7 @@ 
 
 enum
 {
-  CPUID_INDEX_MAX = CPUID_INDEX_24_ECX_1 + 1
+  CPUID_INDEX_MAX = CPUID_INDEX_29_ECX_0 + 1
 };
 
 enum
@@ -348,6 +348,11 @@  enum
 #define bit_cpu_AVX10_V1_AUX	(1u << 2)
 #define bit_cpu_AVX10_V2_AUX	(1u << 3)
 
+/* CPUID_INDEX_29_ECX_0.  */
+
+/* EBX.  */
+#define bit_cpu_APX_NCI_NDD_NF	(1u << 0)
+
 /* CPUID_INDEX_1.  */
 
 /* ECX.  */
@@ -610,6 +615,11 @@  enum
 #define index_AVX10_V1_AUX	CPUID_INDEX_24_ECX_1
 #define index_AVX10_V2_AUX	CPUID_INDEX_24_ECX_1
 
+/* CPUID_INDEX_29_ECX_0.  */
+
+/* EBX.  */
+#define index_cpu_APX_NCI_NDD_NF CPUID_INDEX_29_ECX_0
+
 /* CPUID_INDEX_1.  */
 
 /* ECX.  */
@@ -872,6 +882,11 @@  enum
 #define reg_AVX10_V1_AUX	ecx
 #define reg_AVX10_V2_AUX	ecx
 
+/* CPUID_INDEX_29_ECX_0.  */
+
+/* EBX.  */
+#define reg_APX_NCI_NDD_NF	ebx
+
 /* PREFERRED_FEATURE_INDEX_1.  First define the bitindex values
    sequentially, then define the bit_arch* and index_arch_* lookup
    constants.  */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index c6af1793fe..83c5cbc29e 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -224,6 +224,7 @@  do_test (void)
   CHECK_CPU_FEATURE_PRESENT (AESKLE);
   CHECK_CPU_FEATURE_PRESENT (WIDE_KL);
   CHECK_CPU_FEATURE_PRESENT (PTWRITE);
+  CHECK_CPU_FEATURE_PRESENT (APX_NCI_NDD_NF);
 
   printf ("Possible CPU features:\n");
   CHECK_CPU_FEATURE_ACTIVE (SSE3);
@@ -397,6 +398,7 @@  do_test (void)
   CHECK_CPU_FEATURE_ACTIVE (AESKLE);
   CHECK_CPU_FEATURE_ACTIVE (WIDE_KL);
   CHECK_CPU_FEATURE_ACTIVE (PTWRITE);
+  CHECK_CPU_FEATURE_ACTIVE (APX_NCI_NDD_NF);
 
   unsigned int version = x86_get_avx10_version ();
   printf ("AVX10 version: %d\n", version);
-- 
2.55.0