From patchwork Tue Dec 13 18:48:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Senkevich X-Patchwork-Id: 18431 Received: (qmail 109259 invoked by alias); 13 Dec 2016 18:49:05 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 109248 invoked by uid 89); 13 Dec 2016 18:49:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=andrew.senkevich@intel.com, andrewsenkevichintelcom, Intel, Hx-languages-length:2865 X-HELO: mail-vk0-f51.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=MENHigVlxsz8pDHBslm0bUALjgP0AGs0TNdE6ZOeXJE=; b=Bho+DZBnHsAC0Gh1VPjjeHADna0GRqfvSoEUTA9Dpx6P3QXYEbyrvXmURlO21olOzf ldw6wXQappvJkfVfE9dl4d24XtPD8LZvqquz8HYOqh3Gs4se+ELqo2GClg3+ZtC2B7ju isw+j0q7d+6UDsoAkE+R0juqdmBZpvXf7/Zbnih5IysHeSqaGLVlMPepBGTM4Oh82UiC su9McEgdwSiHBuVOV0wSGn2d0RsGj4tSI2gJXP2eqD2POYLkEbF1vaFTvUBTWVVewpMo G3pWSPyGzK77HH2F+nNK1VkfjWOPpvavy9hBhojblCrqZXBRGnUkgPjlLRFHnm13YKJz /t1Q== X-Gm-Message-State: AKaTC03WpuL+p4xGG4h6alSEykf9lci7RP56IC3mimt+R7VWOv2dDcPYruPF8oMoHov84BM1C7IoY5I20Kl6sQ== X-Received: by 10.31.88.1 with SMTP id m1mr42078748vkb.83.1481654933022; Tue, 13 Dec 2016 10:48:53 -0800 (PST) MIME-Version: 1.0 From: Andrew Senkevich Date: Tue, 13 Dec 2016 21:48:22 +0300 Message-ID: Subject: [PATCH][x86_64] Disable TSX on some Haswell processors To: libc-alpha Cc: Andi Kleen , "Carlos O'Donell" Hi, this is a workaround which disables TSX on some Haswell processors to avoid TSX on kernel's that weren't updated with the latest microcode package (which is needed to disable TSX by default due to errata). Is this patch Ok? 2016-12-13 Andrew Senkevich * sysdeps/x86/cpu-features.c (get_common_indeces): Add stepping identification. (init_cpu_features): Add handle of Haswell. --- WBR, Andrew diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index e228a76..a903390 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -22,7 +22,7 @@ static void get_common_indeces (struct cpu_features *cpu_features, unsigned int *family, unsigned int *model, - unsigned int *extended_model) + unsigned int *extended_model, unsigned int *stepping) { if (family) { @@ -34,6 +34,7 @@ get_common_indeces (struct cpu_features *cpu_features, *family = (eax >> 8) & 0x0f; *model = (eax >> 4) & 0x0f; *extended_model = (eax >> 12) & 0xf0; + *stepping = eax & 0x0f; if (*family == 0x0f) { *family += (eax >> 20) & 0xff; @@ -116,11 +117,12 @@ init_cpu_features (struct cpu_features *cpu_features) /* This spells out "GenuineIntel". */ if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69) { - unsigned int extended_model; + unsigned int extended_model, stepping; kind = arch_kind_intel; - get_common_indeces (cpu_features, &family, &model, &extended_model); + get_common_indeces (cpu_features, &family, &model, &extended_model, + &stepping); if (family == 0x06) { @@ -201,6 +203,19 @@ init_cpu_features (struct cpu_features *cpu_features) | bit_arch_Fast_Unaligned_Copy | bit_arch_Prefer_PMINUB_for_stringop); break; + + case 0x3f: + if (stepping >= 4) + break; + case 0x3c: + case 0x45: + case 0x46: + /* Disable Intel TSX on Haswell processors (except Xeon E7 v3) + to avoid TSX on kernel's that weren't updated with the latest + microcode package (which disables broken feature + by default). */ + cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_cpu_RTM); + break; } } @@ -227,11 +242,12 @@ init_cpu_features (struct cpu_features *cpu_features) /* This spells out "AuthenticAMD". */ else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) { - unsigned int extended_model; + unsigned int extended_model, stepping; kind = arch_kind_amd; - get_common_indeces (cpu_features, &family, &model, &extended_model); + get_common_indeces (cpu_features, &family, &model, &extended_model, + &stepping); ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx; @@ -268,7 +284,7 @@ init_cpu_features (struct cpu_features *cpu_features) else { kind = arch_kind_other; - get_common_indeces (cpu_features, NULL, NULL, NULL); + get_common_indeces (cpu_features, NULL, NULL, NULL, NULL); } /* Support i586 if CX8 is available. */