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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(136003)(396003)(346002)(376002)(40470700004)(46966006)(36840700001)(36860700001)(8936002)(40480700001)(55016003)(40460700003)(478600001)(47076005)(186003)(52536014)(336012)(6506007)(7696005)(5660300002)(26005)(83380400001)(2906002)(33656002)(81166007)(9686003)(6916009)(86362001)(82740400003)(316002)(356005)(82310400005)(8676002)(70206006)(70586007)(41300700001)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2022 14:08:35.1979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1016d293-71e9-41d0-9e6a-08da69902b8f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT063.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR2PR08MB4763 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Wilco Dijkstra via Libc-alpha From: Wilco Dijkstra Reply-To: Wilco Dijkstra Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" After the cleanup, it is now easy to switch to standard builtin atomics by removing the !USE_ATOMIC_COMPILER_BUILTINS clause in atomic.h. A small adjustment is needed for m68k since it incorrectly claims to support lock-free 64-bit atomics. Passes buildmanyglibc and regression testing on AArch64. diff --git a/include/atomic.h b/include/atomic.h index 0f31ea77ba2095ea461bf84f89c9987317f63b35..bf6417621a34458a1d7585ee6a7a24cea6670a07 100644 --- a/include/atomic.h +++ b/include/atomic.h @@ -266,9 +266,6 @@ C11. Usually, a function named atomic_OP_MO(args) is equivalent to C11's atomic_OP_explicit(args, memory_order_MO); exceptions noted below. */ -/* Each arch can request to use compiler built-ins for C11 atomics. If it - does, all atomics will be based on these. */ -#if USE_ATOMIC_COMPILER_BUILTINS /* We require 32b atomic operations; some archs also support 64b atomic operations. */ @@ -383,166 +380,6 @@ void __atomic_link_error (void); ({ __atomic_check_size((mem)); \ __atomic_fetch_xor ((mem), (operand), __ATOMIC_RELEASE); }) -#else /* !USE_ATOMIC_COMPILER_BUILTINS */ - -/* By default, we assume that read, write, and full barriers are equivalent - to acquire, release, and seq_cst barriers. Archs for which this does not - hold have to provide custom definitions of the fences. */ -# ifndef atomic_thread_fence_acquire -# define atomic_thread_fence_acquire() atomic_read_barrier () -# endif -# ifndef atomic_thread_fence_release -# define atomic_thread_fence_release() atomic_write_barrier () -# endif -# ifndef atomic_thread_fence_seq_cst -# define atomic_thread_fence_seq_cst() atomic_full_barrier () -# endif - -# ifndef atomic_load_relaxed -# define atomic_load_relaxed(mem) \ - ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \ - __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \ - __atg100_val; }) -# endif -# ifndef atomic_load_acquire -# define atomic_load_acquire(mem) \ - ({ __typeof (*(mem)) __atg101_val = atomic_load_relaxed (mem); \ - atomic_thread_fence_acquire (); \ - __atg101_val; }) -# endif - -# ifndef atomic_store_relaxed -/* XXX Use inline asm here? */ -# define atomic_store_relaxed(mem, val) do { *(mem) = (val); } while (0) -# endif -# ifndef atomic_store_release -# define atomic_store_release(mem, val) \ - do { \ - atomic_thread_fence_release (); \ - atomic_store_relaxed ((mem), (val)); \ - } while (0) -# endif - -/* On failure, this CAS has memory_order_relaxed semantics. */ -/* XXX This potentially has one branch more than necessary, but archs - currently do not define a CAS that returns both the previous value and - the success flag. */ -# ifndef atomic_compare_exchange_weak_acquire -# define atomic_compare_exchange_weak_acquire(mem, expected, desired) \ - ({ typeof (*(expected)) __atg102_expected = *(expected); \ - *(expected) = \ - atomic_compare_and_exchange_val_acq ((mem), (desired), *(expected)); \ - *(expected) == __atg102_expected; }) -# endif -# ifndef atomic_compare_exchange_weak_relaxed -/* XXX Fall back to CAS with acquire MO because archs do not define a weaker - CAS. */ -# define atomic_compare_exchange_weak_relaxed(mem, expected, desired) \ - atomic_compare_exchange_weak_acquire ((mem), (expected), (desired)) -# endif -# ifndef atomic_compare_exchange_weak_release -# define atomic_compare_exchange_weak_release(mem, expected, desired) \ - ({ typeof (*(expected)) __atg103_expected = *(expected); \ - *(expected) = \ - atomic_compare_and_exchange_val_rel ((mem), (desired), *(expected)); \ - *(expected) == __atg103_expected; }) -# endif - -/* XXX Fall back to acquire MO because archs do not define a weaker - atomic_exchange. */ -# ifndef atomic_exchange_relaxed -# define atomic_exchange_relaxed(mem, val) \ - atomic_exchange_acq ((mem), (val)) -# endif -# ifndef atomic_exchange_acquire -# define atomic_exchange_acquire(mem, val) \ - atomic_exchange_acq ((mem), (val)) -# endif -# ifndef atomic_exchange_release -# define atomic_exchange_release(mem, val) \ - atomic_exchange_rel ((mem), (val)) -# endif - -# ifndef atomic_fetch_add_acquire -# define atomic_fetch_add_acquire(mem, operand) \ - atomic_exchange_and_add_acq ((mem), (operand)) -# endif -# ifndef atomic_fetch_add_relaxed -/* XXX Fall back to acquire MO because the MO semantics of - atomic_exchange_and_add are not documented; the generic version falls back - to atomic_exchange_and_add_acq if atomic_exchange_and_add is not defined, - and vice versa. */ -# define atomic_fetch_add_relaxed(mem, operand) \ - atomic_fetch_add_acquire ((mem), (operand)) -# endif -# ifndef atomic_fetch_add_release -# define atomic_fetch_add_release(mem, operand) \ - atomic_exchange_and_add_rel ((mem), (operand)) -# endif -# ifndef atomic_fetch_add_acq_rel -# define atomic_fetch_add_acq_rel(mem, operand) \ - ({ atomic_thread_fence_release (); \ - atomic_exchange_and_add_acq ((mem), (operand)); }) -# endif - -/* XXX Fall back to acquire MO because archs do not define a weaker - atomic_and_val. */ -# ifndef atomic_fetch_and_relaxed -# define atomic_fetch_and_relaxed(mem, operand) \ - atomic_fetch_and_acquire ((mem), (operand)) -# endif -/* XXX The default for atomic_and_val has acquire semantics, but this is not - documented. */ -# ifndef atomic_fetch_and_acquire -# define atomic_fetch_and_acquire(mem, operand) \ - atomic_and_val ((mem), (operand)) -# endif -# ifndef atomic_fetch_and_release -/* XXX This unnecessarily has acquire MO. */ -# define atomic_fetch_and_release(mem, operand) \ - ({ atomic_thread_fence_release (); \ - atomic_and_val ((mem), (operand)); }) -# endif - -/* XXX The default for atomic_or_val has acquire semantics, but this is not - documented. */ -# ifndef atomic_fetch_or_acquire -# define atomic_fetch_or_acquire(mem, operand) \ - atomic_or_val ((mem), (operand)) -# endif -/* XXX Fall back to acquire MO because archs do not define a weaker - atomic_or_val. */ -# ifndef atomic_fetch_or_relaxed -# define atomic_fetch_or_relaxed(mem, operand) \ - atomic_fetch_or_acquire ((mem), (operand)) -# endif -/* XXX Contains an unnecessary acquire MO because archs do not define a weaker - atomic_or_val. */ -# ifndef atomic_fetch_or_release -# define atomic_fetch_or_release(mem, operand) \ - ({ atomic_thread_fence_release (); \ - atomic_fetch_or_acquire ((mem), (operand)); }) -# endif - -# ifndef atomic_fetch_xor_release -/* Failing the atomic_compare_exchange_weak_release reloads the value in - __atg104_expected, so we need only do the XOR again and retry. */ -# define atomic_fetch_xor_release(mem, operand) \ - ({ __typeof (mem) __atg104_memp = (mem); \ - __typeof (*(mem)) __atg104_expected = (*__atg104_memp); \ - __typeof (*(mem)) __atg104_desired; \ - __typeof (*(mem)) __atg104_op = (operand); \ - \ - do \ - __atg104_desired = __atg104_expected ^ __atg104_op; \ - while (__glibc_unlikely \ - (atomic_compare_exchange_weak_release ( \ - __atg104_memp, &__atg104_expected, __atg104_desired) \ - == 0)); \ - __atg104_expected; }) -#endif - -#endif /* !USE_ATOMIC_COMPILER_BUILTINS */ /* This operation does not affect synchronization semantics but can be used in the body of a spin loop to potentially improve its efficiency. */ diff --git a/sysdeps/m68k/m680x0/m68020/atomic-machine.h b/sysdeps/m68k/m680x0/m68020/atomic-machine.h index 8460fb61072dce030957b029d7c180de13089481..529aa0a70abdb6fde367a031b2f11e577af2c914 100644 --- a/sysdeps/m68k/m680x0/m68020/atomic-machine.h +++ b/sysdeps/m68k/m680x0/m68020/atomic-machine.h @@ -15,7 +15,8 @@ License along with the GNU C Library. If not, see . */ -#define __HAVE_64B_ATOMICS 1 +/* GCC does not support lock-free 64-bit atomic_load/store. */ +#define __HAVE_64B_ATOMICS 0 #define USE_ATOMIC_COMPILER_BUILTINS 0 /* XXX Is this actually correct? */