From patchwork Tue Oct 10 15:52:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 23426 X-Patchwork-Delegate: tuliom@linux.vnet.ibm.com Received: (qmail 36671 invoked by alias); 10 Oct 2017 15:52:55 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 36422 invoked by uid 89); 10 Oct 2017 15:52:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-27.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=UD:l, reserved X-HELO: mx0a-001b2d01.pphosted.com To: libc-alpha@sourceware.org From: Paul Clarke Subject: [PATCH] powerpc: fix check-before-set in SET_RESTORE_ROUND Date: Tue, 10 Oct 2017 10:52:47 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17101015-0024-0000-0000-0000175140E3 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007873; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000235; SDB=6.00929167; UDB=6.00467652; IPR=6.00709438; BA=6.00005632; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017476; XFM=3.00000015; UTC=2017-10-10 15:52:49 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17101015-0025-0000-0000-00004D0C219C Message-Id: <81a9460e-368d-997c-0e85-d7d8a0387e46@us.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-10_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710100224 A performance regression was introduced by commit 84d74e427a771906830800e574a72f8d25a954b8 "powerpc: Cleanup fenv_private.h". In the powerpc implementation of SET_RESTORE_ROUND, there is the following code in the "SET" function (slightly simplified): Reviewed-by: Tulio Magno Quites Machado Filho --- old.fenv = fegetenv_register (); new.l = (old.l & _FPU_MASK_TRAPS_RN) | r; (1) if (new.l != old.l) (2) { if ((old.l & _FPU_ALL_TRAPS) != 0) (void) __fe_mask_env (); fesetenv_register (new.fenv); (3) -- Line (1) sets the value of "new" to the current value of FPSCR, but masks off summary bits, exceptions, non-IEEE mode, and rounding mode, then ORs in the new rounding mode. Line (2) compares this new value to the current value in order to avoid setting a new value in the FPSCR (line (3)) unless something significant has changed (exception enables or rounding mode). The summary bits are not germane to the comparison, but are cleared in "new" and preserved in "old", resulting in false negative comparisons, and unnecessarily setting the FPSCR in those cases with associated negative performance impacts. The solution is to treat the summaries identically for "new" and "old": - save them in SET - leave them alone otherwise - restore the saved values in RESTORE Also minor changes: - expand _FPU_MASK_RN to 64bit hex, to match other MASKs - treat bit 52 (left-to-right) as reserved (since it is) 2017-10-10 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_private.h: Fix masks to more properly handle summary bits. --- sysdeps/powerpc/fpu/fenv_private.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index 877f25b..984dff9 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -28,17 +28,16 @@ | _FPU_MASK_XM | _FPU_MASK_IM) /* Mask the rounding mode bits. */ -#define _FPU_MASK_RN (~0x3) +#define _FPU_MASK_RN 0xfffffffffffffffcLL -/* Mask everything but the rounding moded and non-IEEE arithmetic flags. */ -#define _FPU_MASK_NOT_RN_NI 0xffffffff00000007LL +/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */ +#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL /* Mask restore rounding mode and exception enabled. */ -#define _FPU_MASK_TRAPS_RN 0xffffffff1fffff00LL +#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL -/* Mask exception enable but fraction rounded/inexact and FP result/CC - bits. */ -#define _FPU_MASK_FRAC_INEX_RET_CC 0xffffffff1ff80fff +/* Mask FP result flags, preserve fraction rounded/inexact bits. */ +#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL static __always_inline void __libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask,