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(unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJDxvgdX5HFqJHYjAA--.5958S2; Tue, 04 Aug 2026 21:08:39 +0800 (CST) From: mengqinggang To: libc-alpha@sourceware.org Cc: adhemerval.zanella@linaro.org, xuchenghua@loongson.cn, caiyinyu@loongson.cn, chenglulu@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, hejinyang@loongson.cn, mengqinggang@loongson.cn Subject: [RFC PATCH] LoongArch: Fix intermittent nptl/tst-cancel32 failure Date: Tue, 4 Aug 2026 21:05:32 +0800 Message-Id: <20260804130533.594873-1-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CM-TRANSID: qMiowJDxvgdX5HFqJHYjAA--.5958S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org The nptl/tst-cancel32 test fails intermittently on LoongArch with SIGSEGV at __longjmp: 0x7ffff7de7f6c <__longjmp+28> rotri.d $sp, $t0, 0x11 0x7ffff7de7f70 <__longjmp+32> xor $sp, $sp, $t1 If the thread is cancelled between the rotri.d and xor, an incomplete sp register causes the SIGSEGV. Add a temporary register to avoid this issue. --- sysdeps/loongarch/__longjmp.S | 4 ++-- sysdeps/unix/sysv/linux/loongarch/pointer_guard-asm.h | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/sysdeps/loongarch/__longjmp.S b/sysdeps/loongarch/__longjmp.S index 191f03320a..302cb6894a 100644 --- a/sysdeps/loongarch/__longjmp.S +++ b/sysdeps/loongarch/__longjmp.S @@ -23,9 +23,9 @@ ENTRY (__longjmp) #ifdef PTR_MANGLE REG_L t0, a0, 0*SZREG - PTR_DEMANGLE (ra, t0, t1) + PTR_DEMANGLE (ra, t0, t1, t2) REG_L t0, a0, 1*SZREG - PTR_DEMANGLE2 (sp, t0, t1) + PTR_DEMANGLE2 (sp, t0, t1, t2) #else REG_L ra, a0, 0*SZREG REG_L sp, a0, 1*SZREG diff --git a/sysdeps/unix/sysv/linux/loongarch/pointer_guard-asm.h b/sysdeps/unix/sysv/linux/loongarch/pointer_guard-asm.h index 75498545cb..8fe7d1e15a 100644 --- a/sysdeps/unix/sysv/linux/loongarch/pointer_guard-asm.h +++ b/sysdeps/unix/sysv/linux/loongarch/pointer_guard-asm.h @@ -32,16 +32,16 @@ # define PTR_MANGLE(dst, src, guard) \ PTR_MANGLE_LOAD (guard); \ PTR_MANGLE2 (dst, src, guard); -# define PTR_DEMANGLE(dst, src, guard) \ +# define PTR_DEMANGLE(dst, src, guard, tmp) \ PTR_MANGLE_LOAD (guard); \ - PTR_DEMANGLE2 (dst, src, guard); + PTR_DEMANGLE2 (dst, src, guard, tmp); /* Use PTR_MANGLE2 for efficiency if guard is already loaded. */ # define PTR_MANGLE2(dst, src, guard) \ xor dst, src, guard; \ rotri.d dst, dst, 47; -# define PTR_DEMANGLE2(dst, src, guard) \ - rotri.d dst, src, 17; \ - xor dst, dst, guard; +# define PTR_DEMANGLE2(dst, src, guard, tmp) \ + rotri.d tmp, src, 17; \ + xor dst, tmp, guard; #endif #endif /* POINTER_GUARD_ASM_H */