diff mbox series

[v4,06/17] riscv/cfi: Add prctl definitions for RISC-V CFI

Message ID	20260526061703.2188042-7-jesse.huang@sifive.com (mailing list archive)
State	New
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 70E304BA79A1 From: Jesse Huang <jesse.huang@sifive.com> To: libc-alpha@sourceware.org Cc: andrew@sifive.com, darius@bluespec.com, debug@rivosinc.com, jeffreyalaw@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, Jesse Huang <jesse.huang@sifive.com> Subject: [PATCH v4 06/17] riscv/cfi: Add prctl definitions for RISC-V CFI Date: Mon, 25 May 2026 23:16:52 -0700 Message-Id: <20260526061703.2188042-7-jesse.huang@sifive.com> In-Reply-To: <20260526061703.2188042-1-jesse.huang@sifive.com> References: <20260526061703.2188042-1-jesse.huang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org
Series	Support RISC-V Control Flow Integrifty (CFI) \| [v4,00/17] Support RISC-V Control Flow Integrifty (CFI) [v4,01/17] riscv: Add --enable-cfi option for controlling cfi features [v4,02/17] riscv/cfi: Setup necessary options for enable-cfi option [v4,03/17] riscv: Add GNU property definitions for RISC-V CFI [v4,04/17] riscv: Adjust assembly routines to support landing pad [v4,05/17] riscv: Introduce feature variables for holding RISC-V GNU properties [v4,06/17] riscv/cfi: Add prctl definitions for RISC-V CFI [v4,07/17] riscv/cfi: Enable CFI on static binaries [v4,08/17] riscv/cfi: Enable CFI on dynamic binaries [v4,09/17] riscv/cfi: introduce tunables for CFI features [v4,10/17] riscv/cfi: Adjust setjmp/longjmp for shadow stack to work [v4,11/17] riscv/cfi: Support locking/disabling CFI and move OS depedent code [v4,12/17] riscv/cfi: Store shadow stack information in TLS [v4,13/17] riscv/cfi: Add internal sigset_t union and use it for both ucontext/jmpbuf [v4,14/17] riscv/cfi: Add __allocate_shadow_stack for mapping new shadow stack [v4,15/17] riscv/cfi: Support ucontext under CFI [v4,16/17] riscv/cfi: Add __INDIRECT_RETURN attribute to swapcontext [v4,17/17] riscv/cfi: Switch to new prctl interface

Checks

Context	Check	Description
redhat-pt-bot/TryBot-apply_patch	success	Patch applied to master at the time it was sent
linaro-tcwg-bot/tcwg_glibc_build--master-arm	success	Build passed
linaro-tcwg-bot/tcwg_glibc_build--master-aarch64	success	Build passed
linaro-tcwg-bot/tcwg_glibc_check--master-aarch64	success	Test passed
linaro-tcwg-bot/tcwg_glibc_check--master-arm	fail	Patch failed to apply

Commit Message

Jesse Huang May 26, 2026, 6:16 a.m. UTC

  These operations are for setting/retrieving/locking the status of the
landing pad and the shadow stack extensions.
---
 .../unix/sysv/linux/riscv/include/asm/prctl.h | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h

Comments

Deepak Gupta May 26, 2026, 6:33 p.m. UTC | #1

Hi Jesse,

comments inline.

On Mon, May 25, 2026 at 11:18 PM Jesse Huang <jesse.huang@sifive.com> wrote:
>
> These operations are for setting/retrieving/locking the status of the
> landing pad and the shadow stack extensions.
> ---
>  .../unix/sysv/linux/riscv/include/asm/prctl.h | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
>  create mode 100644 sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>
> diff --git a/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> new file mode 100644
> index 0000000000..091a21b70d
> --- /dev/null
> +++ b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> @@ -0,0 +1,48 @@
> +/*
> + * Get the current shadow stack configuration for the current thread,
> + * this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
> + */
> +#define PR_GET_SHADOW_STACK_STATUS     74
> +
> +/*
> + * Set the current shadow stack configuration.  Enabling the shadow
> + * stack will cause a shadow stack to be allocated for the thread.
> + */
> +#define PR_SET_SHADOW_STACK_STATUS     75
> +# define PR_SHADOW_STACK_ENABLE                (1UL << 0)
> +# define PR_SHADOW_STACK_WRITE         (1UL << 1)
> +# define PR_SHADOW_STACK_PUSH          (1UL << 2)
> +
> +/*
> + * Prevent further changes to the specified shadow stack
> + * configuration.  All bits may be locked via this call, including
> + * undefined bits.
> + */
> +#define PR_LOCK_SHADOW_STACK_STATUS    76
> +
> +/*
> + * Get the current indirect branch tracking configuration for the current
> + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
> + */
> +#define PR_GET_INDIR_BR_LP_STATUS      79

I think paul has sent out patches for changing names of prctls for landing pad.
Value remains same but names are being changed.

> +
> +/*
> + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
> + * enable cpu feature for user thread, to track all indirect branches and ensure
> + * they land on arch defined landing pad instruction.
> + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction.
> + * arch64 - If enabled, an indirect branch must land on `BTI` instruction.
> + * riscv - If enabled, an indirect branch must land on `lpad` instruction.
> + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
> + * branches will no more be tracked by cpu to land on arch defined landing pad
> + * instruction.
> + */
> +#define PR_SET_INDIR_BR_LP_STATUS      80
> +# define PR_INDIR_BR_LP_ENABLE         (1UL << 0)
> +
> +/*
> + * Prevent further changes to the specified indirect branch tracking
> + * configuration.  All bits may be locked via this call, including
> + * undefined bits.
> + */
> +#define PR_LOCK_INDIR_BR_LP_STATUS     81
> --
> 2.43.7
>

Jesse Huang May 28, 2026, 3:13 a.m. UTC | #2

Hi Deepak,

I have a separate commit for updating the interfaces, it's the last one in
this series. Please check it out.
Or you think is better to squash it into the these older commits?

Thanks,

On Wed, May 27, 2026 at 2:33 AM Deepak Gupta <debug@rivosinc.com> wrote:

> Hi Jesse,
>
> comments inline.
>
> On Mon, May 25, 2026 at 11:18 PM Jesse Huang <jesse.huang@sifive.com>
> wrote:
> >
> > These operations are for setting/retrieving/locking the status of the
> > landing pad and the shadow stack extensions.
> > ---
> >  .../unix/sysv/linux/riscv/include/asm/prctl.h | 48 +++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >  create mode 100644 sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> >
> > diff --git a/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> > new file mode 100644
> > index 0000000000..091a21b70d
> > --- /dev/null
> > +++ b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
> > @@ -0,0 +1,48 @@
> > +/*
> > + * Get the current shadow stack configuration for the current thread,
> > + * this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
> > + */
> > +#define PR_GET_SHADOW_STACK_STATUS     74
> > +
> > +/*
> > + * Set the current shadow stack configuration.  Enabling the shadow
> > + * stack will cause a shadow stack to be allocated for the thread.
> > + */
> > +#define PR_SET_SHADOW_STACK_STATUS     75
> > +# define PR_SHADOW_STACK_ENABLE                (1UL << 0)
> > +# define PR_SHADOW_STACK_WRITE         (1UL << 1)
> > +# define PR_SHADOW_STACK_PUSH          (1UL << 2)
> > +
> > +/*
> > + * Prevent further changes to the specified shadow stack
> > + * configuration.  All bits may be locked via this call, including
> > + * undefined bits.
> > + */
> > +#define PR_LOCK_SHADOW_STACK_STATUS    76
> > +
> > +/*
> > + * Get the current indirect branch tracking configuration for the
> current
> > + * thread, this will be the value configured via
> PR_SET_INDIR_BR_LP_STATUS.
> > + */
> > +#define PR_GET_INDIR_BR_LP_STATUS      79
>
> I think paul has sent out patches for changing names of prctls for landing
> pad.
> Value remains same but names are being changed.
>
> > +
> > +/*
> > + * Set the indirect branch tracking configuration.
> PR_INDIR_BR_LP_ENABLE will
> > + * enable cpu feature for user thread, to track all indirect branches
> and ensure
> > + * they land on arch defined landing pad instruction.
> > + * x86 - If enabled, an indirect branch must land on `ENDBRANCH`
> instruction.
> > + * arch64 - If enabled, an indirect branch must land on `BTI`
> instruction.
> > + * riscv - If enabled, an indirect branch must land on `lpad`
> instruction.
> > + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and
> indirect
> > + * branches will no more be tracked by cpu to land on arch defined
> landing pad
> > + * instruction.
> > + */
> > +#define PR_SET_INDIR_BR_LP_STATUS      80
> > +# define PR_INDIR_BR_LP_ENABLE         (1UL << 0)
> > +
> > +/*
> > + * Prevent further changes to the specified indirect branch tracking
> > + * configuration.  All bits may be locked via this call, including
> > + * undefined bits.
> > + */
> > +#define PR_LOCK_INDIR_BR_LP_STATUS     81
> > --
> > 2.43.7
> >
>

Deepak Gupta May 28, 2026, 4:30 p.m. UTC | #3

I think squashing is a better thing to do here.

On Wed, May 27, 2026 at 8:13 PM Jesse Huang <jesse.huang@sifive.com> wrote:
>
> Hi Deepak,
>
> I have a separate commit for updating the interfaces, it's the last one in this series. Please check it out.
> Or you think is better to squash it into the these older commits?
>
> Thanks,
>
> On Wed, May 27, 2026 at 2:33 AM Deepak Gupta <debug@rivosinc.com> wrote:
>>
>> Hi Jesse,
>>
>> comments inline.
>>
>> On Mon, May 25, 2026 at 11:18 PM Jesse Huang <jesse.huang@sifive.com> wrote:
>> >
>> > These operations are for setting/retrieving/locking the status of the
>> > landing pad and the shadow stack extensions.
>> > ---
>> >  .../unix/sysv/linux/riscv/include/asm/prctl.h | 48 +++++++++++++++++++
>> >  1 file changed, 48 insertions(+)
>> >  create mode 100644 sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>> >
>> > diff --git a/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>> > new file mode 100644
>> > index 0000000000..091a21b70d
>> > --- /dev/null
>> > +++ b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
>> > @@ -0,0 +1,48 @@
>> > +/*
>> > + * Get the current shadow stack configuration for the current thread,
>> > + * this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
>> > + */
>> > +#define PR_GET_SHADOW_STACK_STATUS     74
>> > +
>> > +/*
>> > + * Set the current shadow stack configuration.  Enabling the shadow
>> > + * stack will cause a shadow stack to be allocated for the thread.
>> > + */
>> > +#define PR_SET_SHADOW_STACK_STATUS     75
>> > +# define PR_SHADOW_STACK_ENABLE                (1UL << 0)
>> > +# define PR_SHADOW_STACK_WRITE         (1UL << 1)
>> > +# define PR_SHADOW_STACK_PUSH          (1UL << 2)
>> > +
>> > +/*
>> > + * Prevent further changes to the specified shadow stack
>> > + * configuration.  All bits may be locked via this call, including
>> > + * undefined bits.
>> > + */
>> > +#define PR_LOCK_SHADOW_STACK_STATUS    76
>> > +
>> > +/*
>> > + * Get the current indirect branch tracking configuration for the current
>> > + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
>> > + */
>> > +#define PR_GET_INDIR_BR_LP_STATUS      79
>>
>> I think paul has sent out patches for changing names of prctls for landing pad.
>> Value remains same but names are being changed.
>>
>> > +
>> > +/*
>> > + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
>> > + * enable cpu feature for user thread, to track all indirect branches and ensure
>> > + * they land on arch defined landing pad instruction.
>> > + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction.
>> > + * arch64 - If enabled, an indirect branch must land on `BTI` instruction.
>> > + * riscv - If enabled, an indirect branch must land on `lpad` instruction.
>> > + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
>> > + * branches will no more be tracked by cpu to land on arch defined landing pad
>> > + * instruction.
>> > + */
>> > +#define PR_SET_INDIR_BR_LP_STATUS      80
>> > +# define PR_INDIR_BR_LP_ENABLE         (1UL << 0)
>> > +
>> > +/*
>> > + * Prevent further changes to the specified indirect branch tracking
>> > + * configuration.  All bits may be locked via this call, including
>> > + * undefined bits.
>> > + */
>> > +#define PR_LOCK_INDIR_BR_LP_STATUS     81
>> > --
>> > 2.43.7
>> >

diff mbox series

Patch

diff --git a/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
new file mode 100644
index 0000000000..091a21b70d
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/riscv/include/asm/prctl.h
@@ -0,0 +1,48 @@ 
+/*
+ * Get the current shadow stack configuration for the current thread,
+ * this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
+ */
+#define PR_GET_SHADOW_STACK_STATUS	74
+
+/*
+ * Set the current shadow stack configuration.  Enabling the shadow
+ * stack will cause a shadow stack to be allocated for the thread.
+ */
+#define PR_SET_SHADOW_STACK_STATUS	75
+# define PR_SHADOW_STACK_ENABLE		(1UL << 0)
+# define PR_SHADOW_STACK_WRITE		(1UL << 1)
+# define PR_SHADOW_STACK_PUSH		(1UL << 2)
+
+/*
+ * Prevent further changes to the specified shadow stack
+ * configuration.  All bits may be locked via this call, including
+ * undefined bits.
+ */
+#define PR_LOCK_SHADOW_STACK_STATUS	76
+
+/*
+ * Get the current indirect branch tracking configuration for the current
+ * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS.
+ */
+#define PR_GET_INDIR_BR_LP_STATUS	79
+
+/*
+ * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE will
+ * enable cpu feature for user thread, to track all indirect branches and ensure
+ * they land on arch defined landing pad instruction.
+ * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instruction.
+ * arch64 - If enabled, an indirect branch must land on `BTI` instruction.
+ * riscv - If enabled, an indirect branch must land on `lpad` instruction.
+ * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect
+ * branches will no more be tracked by cpu to land on arch defined landing pad
+ * instruction.
+ */
+#define PR_SET_INDIR_BR_LP_STATUS	80
+# define PR_INDIR_BR_LP_ENABLE		(1UL << 0)
+
+/*
+ * Prevent further changes to the specified indirect branch tracking
+ * configuration.  All bits may be locked via this call, including
+ * undefined bits.
+ */
+#define PR_LOCK_INDIR_BR_LP_STATUS	81