diff mbox series

[v2] RISC-V: Use builtin for ffs and ffsll while supported extension available

Message ID 20241108134143.327-1-julian.oerv@isrc.iscas.ac.cn
State New
Headers
Series [v2] RISC-V: Use builtin for ffs and ffsll while supported extension available |

Checks

Context Check Description
redhat-pt-bot/TryBot-apply_patch success Patch applied to master at the time it was sent
linaro-tcwg-bot/tcwg_glibc_build--master-arm success Build passed
redhat-pt-bot/TryBot-32bit success Build for i686
linaro-tcwg-bot/tcwg_glibc_check--master-arm success Test passed
linaro-tcwg-bot/tcwg_glibc_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_glibc_check--master-aarch64 success Test passed

Commit Message

Julian Zhu Nov. 8, 2024, 1:41 p.m. UTC 
  Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`.

Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
---
 sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h

Comments

Julian Zhu Nov. 25, 2024, 3:43 p.m. UTC | #1 
Ping. Thanks.

在 2024/11/8 21:41, Julian Zhu 写道:
> Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`.
> 
> Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
> ---
>   sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++
>   1 file changed, 10 insertions(+)
diff mbox series

Patch

diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h
new file mode 100644
index 0000000000..97d13e9496
--- /dev/null
+++ b/sysdeps/riscv/math-use-builtins-ffs.h
@@ -0,0 +1,10 @@ 
+#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb
+#  define USE_FFS_BUILTIN 1
+#  define USE_FFSLL_BUILTIN 1
+#elif __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb
+#  define USE_FFS_BUILTIN 0
+#  define USE_FFSLL_BUILTIN 1
+#else
+#  define USE_FFS_BUILTIN 0
+#  define USE_FFSLL_BUILTIN 0
+#endif