diff mbox series

[v2,09/15] RISC-V: Add compiler test for Zbb function attribute support

Message ID 20240527111900.1060546-10-christoph.muellner@vrull.eu
State New
Headers
Series RISC-V: Add Zbb-optimized string routines as ifuncs |

Checks

Context Check Description
redhat-pt-bot/TryBot-apply_patch success Patch applied to master at the time it was sent
linaro-tcwg-bot/tcwg_glibc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_glibc_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_glibc_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_glibc_check--master-aarch64 success Testing passed
redhat-pt-bot/TryBot-still_applies warning Patch no longer applies to master

Commit Message

Christoph Müllner May 27, 2024, 11:18 a.m. UTC 
  Target function attributes that allow enabling RISC-V extensions
have been added to GCC and LLVM a few months ago.
This patch adds a configure test to see if the compiler supports
enabling Zbb via this mechanism.

Note, that unknown target attributes just issue a warning, so this
test needs to build with -Werror.

Tested with GCC 13 (fails) and GCC 14 (succeeds).

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 config.h.in                |  3 +++
 sysdeps/riscv/configure    | 27 +++++++++++++++++++++++++++
 sysdeps/riscv/configure.ac | 18 ++++++++++++++++++
 3 files changed, 48 insertions(+)
diff mbox series

Patch

diff --git a/config.h.in b/config.h.in
index 9a83b774fa..10a670441c 100644
--- a/config.h.in
+++ b/config.h.in
@@ -273,6 +273,9 @@ 
 /* PowerPC32 uses fctidz for floating point to long long conversions.  */
 #define HAVE_PPC_FCTIDZ 0
 
+/* RISC-V function attributes for Zbb.  */
+#define HAVE_RISCV_FATTRIBUTE_ZBB 0
+
 /* Define if PIE is unsupported.  */
 #undef PIE_UNSUPPORTED
 
diff --git a/sysdeps/riscv/configure b/sysdeps/riscv/configure
index c8f01709f8..e0f57fcf9b 100644
--- a/sysdeps/riscv/configure
+++ b/sysdeps/riscv/configure
@@ -80,3 +80,30 @@  if test "$libc_cv_static_pie_on_riscv" = yes; then
   printf "%s\n" "#define SUPPORT_STATIC_PIE 1" >>confdefs.h
 
 fi
+
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for RISC-V Zbb target attribute support" >&5
+printf %s "checking for RISC-V Zbb target attribute support... " >&6; }
+if test ${libc_cv_compiler_fattribute_zbb+y}
+then :
+  printf %s "(cached) " >&6
+else $as_nop
+  cat > conftest.c <<EOF
+__attribute__((target("arch=+zbb")))
+void foo() {}
+EOF
+libc_cv_compiler_fattribute_zbb=no
+if ${CC-cc} -Werror -c conftest.c -o /dev/null 1>&5 \
+   2>&5 ; then
+  libc_cv_compiler_fattribute_zbb=yes
+fi
+rm -f conftest*
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_compiler_fattribute_zbb" >&5
+printf "%s\n" "$libc_cv_compiler_fattribute_zbb" >&6; }
+if test "$libc_cv_compiler_fattribute_zbb" = yes; then
+  printf "%s\n" "#define HAVE_RISCV_FATTRIBUTE_ZBB 1" >>confdefs.h
+
+fi
+config_vars="$config_vars
+have-fattribute-zbb-support = $libc_cv_compiler_fattribute_zbb"
+
diff --git a/sysdeps/riscv/configure.ac b/sysdeps/riscv/configure.ac
index ee3d1ed014..a7e16dcf83 100644
--- a/sysdeps/riscv/configure.ac
+++ b/sysdeps/riscv/configure.ac
@@ -43,3 +43,21 @@  EOF
 if test "$libc_cv_static_pie_on_riscv" = yes; then
   AC_DEFINE(SUPPORT_STATIC_PIE)
 fi
+
+dnl Test if we have Zbb via function attributes
+AC_CACHE_CHECK([for RISC-V Zbb target attribute support],
+		libc_cv_compiler_fattribute_zbb, [dnl
+cat > conftest.c <<EOF
+__attribute__((target("arch=+zbb")))
+void foo() {}
+EOF
+libc_cv_compiler_fattribute_zbb=no
+if ${CC-cc} -Werror -c conftest.c -o /dev/null 1>&AS_MESSAGE_LOG_FD \
+   2>&AS_MESSAGE_LOG_FD ; then
+  libc_cv_compiler_fattribute_zbb=yes
+fi
+rm -f conftest*])
+if test "$libc_cv_compiler_fattribute_zbb" = yes; then
+  AC_DEFINE(HAVE_RISCV_FATTRIBUTE_ZBB)
+fi
+LIBC_CONFIG_VAR([have-fattribute-zbb-support], [$libc_cv_compiler_fattribute_zbb])