[RFC,1/3] RISC-V: Sync hwprobe: Sync extension bits with Linux 6.8

Message ID 20240418094635.3502009-2-christoph.muellner@vrull.eu
State Rejected
Headers
Series RISC-V: Use WRS.STO for atomic_spin_nop |

Checks

Context Check Description
redhat-pt-bot/TryBot-apply_patch success Patch applied to master at the time it was sent
linaro-tcwg-bot/tcwg_glibc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_glibc_check--master-aarch64 success Testing passed
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Commit Message

Christoph Müllner April 18, 2024, 9:46 a.m. UTC
  This patch imports additional extension bits for hwprobe
from Linux 6.8.  This patch does not change existing
behaviour as non of the newly defined bits are used
anywhere.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 29 +++++++++++++++++++++
 1 file changed, 29 insertions(+)
  

Patch

diff --git a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
index 8ecb43bb69..4856189f3c 100644
--- a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
+++ b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
@@ -50,6 +50,35 @@  struct riscv_hwprobe {
 #define  RISCV_HWPROBE_EXT_ZBB (1 << 4)
 #define  RISCV_HWPROBE_EXT_ZBS (1 << 5)
 #define  RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
+#define  RISCV_HWPROBE_EXT_ZBC (1 << 7)
+#define  RISCV_HWPROBE_EXT_ZBKB (1 << 8)
+#define  RISCV_HWPROBE_EXT_ZBKC (1 << 9)
+#define  RISCV_HWPROBE_EXT_ZBKX (1 << 10)
+#define  RISCV_HWPROBE_EXT_ZKND (1 << 11)
+#define  RISCV_HWPROBE_EXT_ZKNE (1 << 12)
+#define  RISCV_HWPROBE_EXT_ZKNH (1 << 13)
+#define  RISCV_HWPROBE_EXT_ZKSED (1 << 14)
+#define  RISCV_HWPROBE_EXT_ZKSH (1 << 15)
+#define  RISCV_HWPROBE_EXT_ZKT (1 << 16)
+#define  RISCV_HWPROBE_EXT_ZVBB (1 << 17)
+#define  RISCV_HWPROBE_EXT_ZVBC (1 << 18)
+#define  RISCV_HWPROBE_EXT_ZVKB (1 << 19)
+#define  RISCV_HWPROBE_EXT_ZVKG (1 << 20)
+#define  RISCV_HWPROBE_EXT_ZVKNED (1 << 21)
+#define  RISCV_HWPROBE_EXT_ZVKNHA (1 << 22)
+#define  RISCV_HWPROBE_EXT_ZVKNHB (1 << 23)
+#define  RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
+#define  RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
+#define  RISCV_HWPROBE_EXT_ZVKT (1 << 26)
+#define  RISCV_HWPROBE_EXT_ZFH (1 << 27)
+#define  RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
+#define  RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
+#define  RISCV_HWPROBE_EXT_ZVFH (1 << 30)
+#define  RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
+#define  RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
+#define  RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
+#define  RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
+#define  RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define  RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define  RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)