From patchwork Tue Mar 14 16:25:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 66382 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B37F5385840C for ; Tue, 14 Mar 2023 16:25:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B37F5385840C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1678811146; bh=1gatnBhAZgof08qC1z+lpFUcHFWF+MnZiiqd5RKCMKM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=s1S4OFk2j5F+mKTfX3rR1E3HjM7Awn3Lm17jucwEQcZHUvTxYOkRJt9Ekt1oL0+U3 o/DKvjX6IDdquNpvp756SSCjsbaLVZBMGiznExD84AtKGecWIrhCZM5htj2vH0vTEV Hd8iu2nL3+Om9m9m6dCg16eESMbUsvQp440w8/vs= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by sourceware.org (Postfix) with ESMTPS id 14E4B3858C83 for ; Tue, 14 Mar 2023 16:25:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 14E4B3858C83 Received: by mail-pj1-x102f.google.com with SMTP id j13so195371pjd.1 for ; Tue, 14 Mar 2023 09:25:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678811121; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1gatnBhAZgof08qC1z+lpFUcHFWF+MnZiiqd5RKCMKM=; b=V3QOaIAOHhWQfEW5C3lb7hEOubwPkMOdVHY/VNpmuSIZGsDG3WhIB043T1s+fH99kg P7/MDHhstgsWdMZvOo9P4spbDXCJDWLYEtsVaaNf9Q47wwFUJrVDiwZ2m58kNyu1tI3g TnFmYerMkN1FAwqJ6ghy1TocQNz+pOAIcdC6SNTg+G4tr54FGCbdrS5TfLTtLGgGK4EH aFmHUUP9MKl7tsKUtdauFdm31Ob37AlWFJ1XGrh7mJyYT95Ux2jQTeEKlalsoD7AZvDb a9QpwnJP4I7uEO/nn6ryVoA2NvlkiitYKuHrXTBPmpEveZET7LAYqLwwyqlpui1Jr1iM /BAQ== X-Gm-Message-State: AO0yUKWFAD6DxAL8cAjq9cGacwv0fydFYJ2XhJTwLscYIrvP5qPu1q3e +0bXCBmAuEHqsSSuVqeySzm8BoxlJhuWWjEOL56yrZa/Um2IAERS5za9v5Ng6YyGZn/rT97gSfu YIiEf3ZJyJyZGb3F1nKRMZ7ZM44lp6Gx7tPnVDoctsmh/pIz6vEBCse0+MEg/4+1GSYEcCRNeSr 1zT+xLIA== X-Google-Smtp-Source: AK7set922javqLB0VTbMNQ6fY9uS+n7XEyPNAGjeH/Wnf9Rbx7oaPPKLhX6V3XGWdmMicOMAoSwjlw== X-Received: by 2002:a17:903:1249:b0:19a:ad90:4223 with SMTP id u9-20020a170903124900b0019aad904223mr44191093plh.48.1678811121458; Tue, 14 Mar 2023 09:25:21 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019602274208sm1953051plg.186.2023.03.14.09.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:25:20 -0700 (PDT) To: libc-alpha@sourceware.org, palmer@rivosinc.com, jeffreyalaw@gmail.com, darius@bluespec.com, christoph.muellner@vrull.eu, dj@redhat.com, greentime.hu@sifive.com, vineetg@rivosinc.com Cc: Hsiangkai Wang , Vincent Chen Subject: [PATCH v3] riscv: Resolve symbols directly for symbols with STO_RISCV_VARIANT_CC. Date: Wed, 15 Mar 2023 00:25:12 +0800 Message-Id: <20230314162512.35802-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Libc-alpha From: Kito Cheng Reply-To: Kito Cheng Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" From: Hsiangkai Wang In some cases, we do not want to go through the resolver for function calls. For example, functions with vector arguments will use vector registers to pass arguments. In the resolver, we do not save/restore the vector argument registers for lazy binding efficiency. To avoid ruining the vector arguments, functions with vector arguments will not go through the resolver. To achieve the goal, we will annotate the function symbols with STO_RISCV_VARIANT_CC flag and add DT_RISCV_VARIANT_CC tag in the dynamic section. In the first pass on PLT relocations, we do not set up to call _dl_runtime_resolve. Instead, we resolve the functions directly. Signed-off-by: Hsiangkai Wang Signed-off-by: Vincent Chen Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- Changes: - Update copyright year. - Seperated from the original patchset, it could be used for vector ISA support, but NOT only used for vector support. --- elf/elf.h | 7 +++++++ manual/platform.texi | 6 ++++++ sysdeps/riscv/dl-dtprocnum.h | 21 +++++++++++++++++++++ sysdeps/riscv/dl-machine.h | 26 ++++++++++++++++++++++++++ 4 files changed, 60 insertions(+) create mode 100644 sysdeps/riscv/dl-dtprocnum.h diff --git a/elf/elf.h b/elf/elf.h index 4bc0e4299c..1eef1a7184 100644 --- a/elf/elf.h +++ b/elf/elf.h @@ -3932,6 +3932,13 @@ enum #define R_TILEGX_NUM 130 +/* RISC-V specific values for the Dyn d_tag field. */ +#define DT_RISCV_VARIANT_CC (DT_LOPROC + 1) +#define DT_RISCV_NUM 2 + +/* RISC-V specific values for the st_other field. */ +#define STO_RISCV_VARIANT_CC 0x80 + /* RISC-V ELF Flags */ #define EF_RISCV_RVC 0x0001 #define EF_RISCV_FLOAT_ABI 0x0006 diff --git a/manual/platform.texi b/manual/platform.texi index d5fdc5bd05..a1a740f381 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -121,6 +121,12 @@ when it is not allowed, the priority is set to medium. @node RISC-V @appendixsec RISC-V-specific Facilities +Functions that are lazily bound must be compatible with the standard calling +convention. When a function is annotated with STO_RISCV_VARIANT_CC, it means +this function is not compatible with the standard calling convention. The +dynamic linker will directly resolve it instead of using the lazy binding +mechanism. + Cache management facilities specific to RISC-V systems that implement the Linux ABI are declared in @file{sys/cachectl.h}. diff --git a/sysdeps/riscv/dl-dtprocnum.h b/sysdeps/riscv/dl-dtprocnum.h new file mode 100644 index 0000000000..281c5aadeb --- /dev/null +++ b/sysdeps/riscv/dl-dtprocnum.h @@ -0,0 +1,21 @@ +/* Configuration of lookup functions. RISC-V version. + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +/* Number of extra dynamic section entries for this architecture. By + default there are none. */ +#define DT_THISPROCNUM DT_RISCV_NUM diff --git a/sysdeps/riscv/dl-machine.h b/sysdeps/riscv/dl-machine.h index c0c9bd93ad..0e6c0bb155 100644 --- a/sysdeps/riscv/dl-machine.h +++ b/sysdeps/riscv/dl-machine.h @@ -53,6 +53,9 @@ || (__WORDSIZE == 64 && (type) == R_RISCV_TLS_TPREL64))) \ | (ELF_RTYPE_CLASS_COPY * ((type) == R_RISCV_COPY))) +//* Translate a processor specific dynamic tag to the index in l_info array. */ +#define DT_RISCV(x) (DT_RISCV_##x - DT_LOPROC + DT_NUM) + /* Return nonzero iff ELF header is compatible with the running host. */ static inline int __attribute_used__ elf_machine_matches_host (const ElfW(Ehdr) *ehdr) @@ -281,6 +284,29 @@ elf_machine_lazy_rel (struct link_map *map, struct r_scope_elem *scope[], /* Check for unexpected PLT reloc type. */ if (__glibc_likely (r_type == R_RISCV_JUMP_SLOT)) { + if (__glibc_unlikely (map->l_info[DT_RISCV (VARIANT_CC)] != NULL)) + { + /* Check the symbol table for variant CC symbols. */ + const Elf_Symndx symndx = ELFW(R_SYM) (reloc->r_info); + const ElfW(Sym) *symtab = + (const void *)D_PTR (map, l_info[DT_SYMTAB]); + const ElfW(Sym) *sym = &symtab[symndx]; + if (__glibc_unlikely (sym->st_other & STO_RISCV_VARIANT_CC)) + { + /* Avoid lazy resolution of variant CC symbols. */ + const struct r_found_version *version = NULL; + if (map->l_info[VERSYMIDX (DT_VERSYM)] != NULL) + { + const ElfW(Half) *vernum = + (const void *)D_PTR (map, l_info[VERSYMIDX (DT_VERSYM)]); + version = &map->l_versions[vernum[symndx] & 0x7fff]; + } + elf_machine_rela (map, scope, reloc, sym, version, reloc_addr, + skip_ifunc); + return; + } + } + if (__glibc_unlikely (map->l_mach.plt == 0)) { if (l_addr)