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[111.251.213.204]) by smtp.gmail.com with ESMTPSA id a6-20020a17090a740600b002345ef591dasm8058025pjg.31.2023.03.01.07.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Mar 2023 07:33:05 -0800 (PST) To: libc-alpha@sourceware.org, palmer@dabbelt.com, darius@bluespec.com, andrew@sifive.com, dj@redhat.com Cc: jerry.shih@sifive.com, nick.knight@sifive.com, hongrong.hsu@sifive.com, hau.hsu@sifive.com, kito.cheng@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com Subject: [PATCH 1/4] riscv: Enabling vectorized mem*/str* functions in build time Date: Wed, 1 Mar 2023 23:32:44 +0800 Message-Id: <20230301153247.1499566-2-vincent.chen@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230301153247.1499566-1-vincent.chen@sifive.com> References: <20230301153247.1499566-1-vincent.chen@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Vincent Chen via Libc-alpha From: Vincent Chen Reply-To: Vincent Chen Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Let the build selects the vectorized mem*/str* functions when it detects the compiler supports RISC-V V extension and enables it in this build. We agree that the these vectorized mem*/str* functions should be selected by IFUNC. Therefore, this patch is intended as a **temporary solution** to enable reviewers to evaluate the effectiveness of these vectorized mem*/str* functions. --- scripts/build-many-glibcs.py | 10 ++++++++++ sysdeps/riscv/preconfigure | 19 +++++++++++++++++++ sysdeps/riscv/preconfigure.ac | 18 ++++++++++++++++++ sysdeps/riscv/rv32/rvv/Implies | 2 ++ sysdeps/riscv/rv64/rvv/Implies | 2 ++ 5 files changed, 51 insertions(+) create mode 100644 sysdeps/riscv/rv32/rvv/Implies create mode 100644 sysdeps/riscv/rv64/rvv/Implies diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py index bd212dbc82..8ac86c50f6 100755 --- a/scripts/build-many-glibcs.py +++ b/scripts/build-many-glibcs.py @@ -381,6 +381,11 @@ class Context(object): variant='rv32imafdc-ilp32d', gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d', '--disable-multilib']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imafdcv-ilp32d', + gcc_cfg=['--with-arch=rv32imafdcv', '--with-abi=ilp32d', + '--disable-multilib']) self.add_config(arch='riscv64', os_name='linux-gnu', variant='rv64imac-lp64', @@ -396,6 +401,11 @@ class Context(object): variant='rv64imafdc-lp64d', gcc_cfg=['--with-arch=rv64imafdc', '--with-abi=lp64d', '--disable-multilib']) + self.add_config(arch='riscv64', + os_name='linux-gnu', + variant='rv64imafdcv-lp64d', + gcc_cfg=['--with-arch=rv64imafdcv', '--with-abi=lp64d', + '--disable-multilib']) self.add_config(arch='s390x', os_name='linux-gnu', glibcs=[{}, diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure index 4dedf4b0bb..5ddc195b46 100644 --- a/sysdeps/riscv/preconfigure +++ b/sysdeps/riscv/preconfigure @@ -7,6 +7,7 @@ riscv*) flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2` + vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2` case "$xlen" in 64 | 32) @@ -32,6 +33,24 @@ riscv*) ;; esac + case "$vector" in + __riscv_vector) + case "$flen" in + 64) + float_machine=rvv + ;; + *) + # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only. + ;; + esac + ;; + *) + ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: vector $vector flen $flen float_machine $float_machine" >&5 +$as_echo "$as_me: vector $vector flen $flen float_machine $float_machine" >&6;} + case "$float_abi" in soft) abi_flen=0 diff --git a/sysdeps/riscv/preconfigure.ac b/sysdeps/riscv/preconfigure.ac index a5c30e0dbf..b6b8bb46e4 100644 --- a/sysdeps/riscv/preconfigure.ac +++ b/sysdeps/riscv/preconfigure.ac @@ -7,6 +7,7 @@ riscv*) flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2` + vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2` case "$xlen" in 64 | 32) @@ -32,6 +33,23 @@ riscv*) ;; esac + case "$vector" in + __riscv_vector) + case "$flen" in + 64) + float_machine=rvv + ;; + *) + # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only. + ;; + esac + ;; + *) + ;; + esac + + AC_MSG_NOTICE([vector $vector flen $flen float_machine $float_machine]) + case "$float_abi" in soft) abi_flen=0 diff --git a/sysdeps/riscv/rv32/rvv/Implies b/sysdeps/riscv/rv32/rvv/Implies new file mode 100644 index 0000000000..25ce1df222 --- /dev/null +++ b/sysdeps/riscv/rv32/rvv/Implies @@ -0,0 +1,2 @@ +riscv/rv32/rvd +riscv/rvv diff --git a/sysdeps/riscv/rv64/rvv/Implies b/sysdeps/riscv/rv64/rvv/Implies new file mode 100644 index 0000000000..9993bb30e3 --- /dev/null +++ b/sysdeps/riscv/rv64/rvv/Implies @@ -0,0 +1,2 @@ +riscv/rv64/rvd +riscv/rvv