From patchwork Sun Feb 12 06:52:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiqi Zhang X-Patchwork-Id: 64771 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9EC8D3857365 for ; Sun, 12 Feb 2023 06:53:45 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTP id 1CFC03858D32 for ; Sun, 12 Feb 2023 06:53:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1CFC03858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=isrc.iscas.ac.cn Received: from localhost (unknown [101.6.102.102]) by APP-05 (Coremail) with SMTP id zQCowABnburojOhjsR7OBA--.25001S2; Sun, 12 Feb 2023 14:53:28 +0800 (CST) From: Shiqi Zhang To: libc-alpha@sourceware.org Cc: schwab@linux-m68k.org, Shiqi Zhang Subject: [PATCH v2] riscv: Add macros for FPUCW/fcsr in fpu_control.h Date: Sun, 12 Feb 2023 14:52:15 +0800 Message-Id: <20230212065214.2399-1-shiqi@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowABnburojOhjsR7OBA--.25001S2 X-Coremail-Antispam: 1UD129KBjvJXoW7trWkXr1fCr43Aw18GrW3ZFb_yoW8Gry3pr W3CFy5KFy5tw4aqF4Ik3W8Kr1fXF4UGF1UJ39xCw4xJF4ay3Z7Gr47ur4FvrWUXr1rXayF 9w1UCw1UWF13ArDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUym14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWUuVWrJwAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxG rwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUVMKAUUUUU= X-Originating-IP: [101.6.102.102] X-CM-SenderInfo: 5vkl1xw6lv2u4olvutnvoduhdfq/ X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Add macros for rounding modes and accrued exception flags in order to make controlling fcsr easier for users. Reference: RISC-V Unprivileged Spec v20191213, Section 11.2: Figure 11.2, Table 11.1 & 11.2 --- Fixed careless mistakes in v1 and removed invalid rounding mode DYN. Still, I think these macros should be documented somewhere but I'm not sure where should I doc them. I'll appreciate it if you could give some suggestions. Regards, Shiqi Zhang sysdeps/riscv/fpu_control.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h index c33798c6bb..1dcadd3ea1 100644 --- a/sysdeps/riscv/fpu_control.h +++ b/sysdeps/riscv/fpu_control.h @@ -36,6 +36,20 @@ extern fpu_control_t __fpu_control; # define _FPU_DEFAULT 0 # define _FPU_IEEE _FPU_DEFAULT +/* FPU rounding modes */ +# define _FPU_RM_RNE (0 << 5) +# define _FPU_RM_RTZ (1 << 5) +# define _FPU_RM_RDN (2 << 5) +# define _FPU_RM_RUP (3 << 5) +# define _FPU_RM_RMM (4 << 5) + +/* FPU accrued exception flags */ +# define _FPU_EXCEPT_NV (1 << 4) +# define _FPU_EXCEPT_DZ (1 << 3) +# define _FPU_EXCEPT_OF (1 << 2) +# define _FPU_EXCEPT_UF (1 << 1) +# define _FPU_EXCEPT_NX (1 << 0) + /* Type of the control word. */ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));