diff mbox series

riscv: Add macros for FPUCW in fpu_control.h

Message ID 20230211174916.1455-1-shiqi@isrc.iscas.ac.cn
State Superseded
Headers
Series riscv: Add macros for FPUCW in fpu_control.h |

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent
dj/TryBot-32bit success Build for i686

Commit Message

Shiqi Zhang Feb. 11, 2023, 5:49 p.m. UTC 
  Add macros for rounding modes and accrued exception flags in order to
make controlling FPCSR easier for users.

Reference: RISC-V Unprivileged Spec v20191213, Section 11.2, Table 11.1 & 11.2
---
I'm implementing RISC-V support for netlib/f2c, and found that
there is no definitions for FPCSR flag bits in glibc when writing codes
for FPU exception controls. So I checked them in RISC-V specs and
defined the accrued exception flags and rounding mode flags in this
patch, making it easier for other users to control FPU status.

Also, I think these macros should be documented somewhere but I'm
not sure where should I doc them. I'll appreciate it if you could give
some suggestions.

For copyrights, this patch is covered by an existing copyright
assignment of ISCAS/ISRC so I'm assuming that there shouldn't be a
signed-off-by line in commit message.

 sysdeps/riscv/fpu_control.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Andreas Schwab Feb. 11, 2023, 8:21 p.m. UTC | #1 
On Feb 12 2023, Shiqi Zhang wrote:

> +# define _FPU_RM_DYN (7 << 5)

That is only valid in an insn encoding, not in the fcsr register.

> +/* FPU accrued exception flags */
> +# define _FPU_EXCEPT_NV (1 << 0)
> +# define _FPU_EXCEPT_NZ (1 << 1)
> +# define _FPU_EXCEPT_OF (1 << 2)
> +# define _FPU_EXCEPT_UF (1 << 3)
> +# define _FPU_EXCEPT_NX (1 << 4)

You got them backwards.
Shiqi Zhang Feb. 12, 2023, 6:29 a.m. UTC | #2 
>> +# define _FPU_RM_DYN (7 << 5)
> That is only valid in an insn encoding, not in the fcsr register.
Thank you very much for the tip!
>> +/* FPU accrued exception flags */
>> +# define _FPU_EXCEPT_NV (1 << 0)
>> +# define _FPU_EXCEPT_NZ (1 << 1)
>> +# define _FPU_EXCEPT_OF (1 << 2)
>> +# define _FPU_EXCEPT_UF (1 << 3)
>> +# define _FPU_EXCEPT_NX (1 << 4)
> You got them backwards.

Sorry for my carelessness. I mistakenly assumed that flags in table 11.2
was listed from lower to higher bits. Will send a v2 soon.
diff mbox series

Patch

diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h
index c33798c6bb..5c883be4fe 100644
--- a/sysdeps/riscv/fpu_control.h
+++ b/sysdeps/riscv/fpu_control.h
@@ -36,6 +36,21 @@  extern fpu_control_t __fpu_control;
 # define _FPU_DEFAULT  0
 # define _FPU_IEEE     _FPU_DEFAULT
 
+/* FPU rounding modes */
+# define _FPU_RM_RNE (0 << 5)
+# define _FPU_RM_RTZ (1 << 5)
+# define _FPU_RM_RDN (2 << 5)
+# define _FPU_RM_RUP (3 << 5)
+# define _FPU_RM_RMM (4 << 5)
+# define _FPU_RM_DYN (7 << 5)
+
+/* FPU accrued exception flags */
+# define _FPU_EXCEPT_NV (1 << 0)
+# define _FPU_EXCEPT_NZ (1 << 1)
+# define _FPU_EXCEPT_OF (1 << 2)
+# define _FPU_EXCEPT_UF (1 << 3)
+# define _FPU_EXCEPT_NX (1 << 4)
+
 /* Type of the control word.  */
 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));