diff mbox series

[RFC,05/19] riscv: Introduction of ISA extensions

Message ID	20230207001618.458947-6-christoph.muellner@vrull.eu
State	New
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3AF933858C60 From: Christoph Muellner <christoph.muellner@vrull.eu> To: libc-alpha@sourceware.org, Palmer Dabbelt <palmer@dabbelt.com>, Darius Rad <darius@bluespec.com>, Andrew Waterman <andrew@sifive.com>, DJ Delorie <dj@redhat.com>, Vineet Gupta <vineetg@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>, Jeff Law <jeffreyalaw@gmail.com>, Philipp Tomsich <philipp.tomsich@vrull.eu>, Heiko Stuebner <heiko.stuebner@vrull.eu> Cc: =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu> Subject: [RFC PATCH 05/19] riscv: Introduction of ISA extensions Date: Tue, 7 Feb 2023 01:16:04 +0100 Message-Id: <20230207001618.458947-6-christoph.muellner@vrull.eu> In-Reply-To: <20230207001618.458947-1-christoph.muellner@vrull.eu> References: <20230207001618.458947-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces+patchwork=sourceware.org@sourceware.org>
Series	riscv: ifunc support with optimized mem/str/cpu_relax routines \| [RFC,00/19] riscv: ifunc support with optimized mem/str/cpu_relax routines [RFC,01/19] Inhibit early libcalls before ifunc support is ready [RFC,02/19] riscv: LEAF: Use C_LABEL() to construct the asm name for a C symbol [RFC,03/19] riscv: Add ENTRY_ALIGN() macro [RFC,04/19] riscv: Add hart feature run-time detection framework [RFC,05/19] riscv: Introduction of ISA extensions [RFC,06/19] riscv: Adding ISA string parser for environment variables [RFC,07/19] riscv: hart-features: Add fast_unaligned property [RFC,08/19] riscv: Add (empty) ifunc framework [RFC,09/19] riscv: Add ifunc support for memset [RFC,10/19] riscv: Add accelerated memset routines for RV64 [RFC,11/19] riscv: Add ifunc support for memcpy/memmove [RFC,12/19] riscv: Add accelerated memcpy/memmove routines for RV64 [RFC,13/19] riscv: Add ifunc support for strlen [RFC,14/19] riscv: Add accelerated strlen routine [RFC,15/19] riscv: Add ifunc support for strcmp [RFC,16/19] riscv: Add accelerated strcmp routines [RFC,17/19] riscv: Add ifunc support for strncmp [RFC,18/19] riscv: Add an optimized strncmp routine [RFC,19/19] riscv: Add __riscv_cpu_relax() to allow yielding in busy loops

Checks

Context	Check	Description
dj/TryBot-apply_patch	success	Patch applied to master at the time it was sent

Commit Message

Christoph Müllner Feb. 7, 2023, 12:16 a.m. UTC

  From: Christoph Müllner <christoph.muellner@vrull.eu>

The RISC-V ISA consists of a base ISA and a multitude of optional ISA
extensions. This patch introduces some of them, which are expected
to be relevant in the near future for ifunc-based optimizations in glibc:

* Base (i or e)
* M
* A
* F
* D
* C
* Zicsr
* Zifencei
* G
* Zihintpause
* zicbom
* zicbop
* zicboz
* zawrs
* zba
* zbb
* zbc
* zbs

Given the DSL-like definition it should be trivial to extend the list.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 sysdeps/unix/sysv/linux/riscv/hart-features.h | 27 +++++++
 .../unix/sysv/linux/riscv/isa-extensions.def  | 72 +++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 sysdeps/unix/sysv/linux/riscv/isa-extensions.def

diff mbox series

Patch

diff --git a/sysdeps/unix/sysv/linux/riscv/hart-features.h b/sysdeps/unix/sysv/linux/riscv/hart-features.h
index a417cbc326..dd94685676 100644
--- a/sysdeps/unix/sysv/linux/riscv/hart-features.h
+++ b/sysdeps/unix/sysv/linux/riscv/hart-features.h
@@ -19,8 +19,35 @@ 
 #ifndef _CPU_FEATURES_RISCV_H
 #define _CPU_FEATURES_RISCV_H
 
+#define IS_RV32() \
+	(GLRO (dl_riscv_hart_features).xlen == 32)
+
+#define IS_RV64() \
+	(GLRO (dl_riscv_hart_features).xlen == 64)
+
+#define HAVE_RV(E) \
+	(GLRO (dl_riscv_hart_features).have_ ## E == 1)
+
+#define HAVE_CBOM_BLOCKSIZE(n)	\
+	(GLRO (dl_riscv_hart_features).cbom_blocksize == n)
+
+#define HAVE_CBOZ_BLOCKSIZE(n)	\
+	(GLRO (dl_riscv_hart_features).cboz_blocksize == n)
+
 struct hart_features
 {
+  const char* rt_march;
+  unsigned xlen;
+#define ISA_EXT(e)			\
+  unsigned have_##e:1;
+#define ISA_EXT_GROUP(g, ...)		\
+  unsigned have_##g:1;
+#include "isa-extensions.def"
+
+  const char* rt_cbom_blocksize;
+  unsigned cbom_blocksize;
+  const char* rt_cboz_blocksize;
+  unsigned cboz_blocksize;
 };
 
 #endif /* _CPU_FEATURES_RISCV_H  */
diff --git a/sysdeps/unix/sysv/linux/riscv/isa-extensions.def b/sysdeps/unix/sysv/linux/riscv/isa-extensions.def
new file mode 100644
index 0000000000..eb05823998
--- /dev/null
+++ b/sysdeps/unix/sysv/linux/riscv/isa-extensions.def
@@ -0,0 +1,72 @@ 
+/* ISA extensions of RISC-V.
+   Copyright (C) 2022 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <https://www.gnu.org/licenses/>.  */
+
+/* Define RISC-V ISA extension.  */
+#ifndef ISA_EXT
+# define ISA_EXT(e)
+#endif
+
+/* Define RISC-V ISA extension group.  */
+#ifndef ISA_EXT_GROUP
+# define ISA_EXT_GROUP(...)
+#endif
+
+/*
+ * Here are the ordering rules of extension naming defined by RISC-V
+ * specification :
+ * 1. All extensions should be separated from other multi-letter extensions
+ *    by an underscore.
+ * 2. The first letter following the 'Z' conventionally indicates the most
+ *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
+ *    If multiple 'Z' extensions are named, they should be ordered first
+ *    by category, then alphabetically within a category.
+ * 3. Standard supervisor-level extensions (starts with 'S') should be
+ *    listed after standard unprivileged extensions.  If multiple
+ *    supervisor-level extensions are listed, they should be ordered
+ *    alphabetically.
+ * 4. Non-standard extensions (starts with 'X') must be listed after all
+ *    standard extensions. They must be separated from other multi-letter
+ *    extensions by an underscore.
+ */
+
+ISA_EXT (i)
+ISA_EXT (e)
+
+ISA_EXT (m)
+ISA_EXT (a)
+ISA_EXT (f)
+ISA_EXT (d)
+ISA_EXT (c)
+ISA_EXT (zicsr)
+ISA_EXT (zifencei)
+ISA_EXT_GROUP (g, i, m, a, f, d, zicsr, zifencei)
+
+ISA_EXT (zicbom)
+ISA_EXT (zicbop)
+ISA_EXT (zicboz)
+ISA_EXT (zihintpause)
+
+ISA_EXT (zawrs)
+
+ISA_EXT (zba)
+ISA_EXT (zbb)
+ISA_EXT (zbc)
+ISA_EXT (zbs)
+
+#undef ISA_EXT
+#undef ISA_EXT_GROUP