From patchwork Wed Feb 1 09:52:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Lewis X-Patchwork-Id: 64073 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2A2BA385E004 for ; Wed, 1 Feb 2023 09:54:04 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by sourceware.org (Postfix) with ESMTPS id B86EB3858298 for ; Wed, 1 Feb 2023 09:53:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B86EB3858298 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1035.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so1602396pjq.0 for ; Wed, 01 Feb 2023 01:53:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=9QRIEdtQYkK/8bLxGprIzVRt6w4p+y2z8xdt+cSOcno=; b=JReVtRdIJ7fnBNi8RRbPnW4iqTukXzO3trgrvIXmsCuoUfqXslFHQ4OH07ftSAViLJ HhnG0EmnIvQhMpw7oRwC+ZDUE7WkjcVUsV2CBoiZtw71asyTp4d5/LvTF2jYjELEnO54 6aWnyy6gDaJjFtQMqePhydavfydsMDSdRs8QWpnLFyGQ3qbOn8jWk0WijJdu15WM0DcK ZQIuEIKi7+AipuBSRXWe4JSlw+uSR8XsTRbzAjjzgk66p+9LCCWlBCUNxupj8jpAieQl Oil93vTItboSVRAMT5POo7nTqaacrsKKpQkRIY7GlPQ53C1CgMcpFF44hZWn37rjJ6t2 tUwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9QRIEdtQYkK/8bLxGprIzVRt6w4p+y2z8xdt+cSOcno=; b=HZYpN83qvHadhX/Au5oY0s7QMSJBRMF0UcA5JbYBXFwDHFrGb6KvtdvwSEOp754Zl0 3K7ssnZhjuYJaDg/4L2NLv9nZCmUlnD/E7MMQJ7wjp6cpvNj891X5KmVFj0CXZuuFZ/y 4h6wT4B1cqmK5cNOnKL5HGaPjjFOAoujzpDypQzUeDe9syeZtw4B9onAm9DRIl5bm3jw 8S3bqUmYsoM66QCDGkLLY8+utuRIb7vpcdNv7MWvspXd4CEGDZ7MXKQRKYcO5tv7GzGz LsvsAgLp7EVZr8yQYhjQi41/unnUuxF7IgmE+dFYKxfZcKLYqVbpj9jq42eFIQF2JB2p G+pA== X-Gm-Message-State: AO0yUKXqY0f4N6uTAo3bVqtlCX2ck9JoRvlH9exDDkSuIe79OP9PLdYe hpHYHOhz7pIXM2csjBDYt0W89RqCA+j90kVx X-Google-Smtp-Source: AK7set/ZmC32SmNsCFojDf0FexUkeUPdVTqv47mYafC0CDqDe+ZCJhzfo3XbB+jbKRR1PMaJqo6lUA== X-Received: by 2002:a17:90b:3e82:b0:229:4731:994d with SMTP id rj2-20020a17090b3e8200b002294731994dmr1599010pjb.4.1675245211249; Wed, 01 Feb 2023 01:53:31 -0800 (PST) Received: from slewis-laptop.uk.rivosinc.com ([51.52.155.79]) by smtp.gmail.com with ESMTPSA id h2-20020a17090a470200b00223ed94759csm900985pjg.39.2023.02.01.01.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 01:53:30 -0800 (PST) From: Sergei Lewis To: libc-alpha@sourceware.org Cc: Sergei Lewis Subject: [PATCH 1/2] riscv: sysdeps support for vectorised functions Date: Wed, 1 Feb 2023 09:52:31 +0000 Message-Id: <20230201095232.15942-1-slewis@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This allows the build to detect when the compiler has support for the V extension and its prerequisites enabled in rv64 builds, and select implementations from sysdeps/riscv/rv64/rvv in this case if any are present there. Signed-off-by: Sergei Lewis --- scripts/build-many-glibcs.py | 5 +++++ sysdeps/riscv/preconfigure | 19 +++++++++++++++++++ sysdeps/riscv/preconfigure.ac | 18 ++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py index bd212dbc82..4e5aa2de61 100755 --- a/scripts/build-many-glibcs.py +++ b/scripts/build-many-glibcs.py @@ -396,6 +396,11 @@ class Context(object): variant='rv64imafdc-lp64d', gcc_cfg=['--with-arch=rv64imafdc', '--with-abi=lp64d', '--disable-multilib']) + self.add_config(arch='riscv64', + os_name='linux-gnu', + variant='rv64imafdcv-lp64d', + gcc_cfg=['--with-arch=rv64imafdcv', '--with-abi=lp64d', + '--disable-multilib']) self.add_config(arch='s390x', os_name='linux-gnu', glibcs=[{}, diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure index 4dedf4b0bb..5ddc195b46 100644 --- a/sysdeps/riscv/preconfigure +++ b/sysdeps/riscv/preconfigure @@ -7,6 +7,7 @@ riscv*) flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2` + vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2` case "$xlen" in 64 | 32) @@ -32,6 +33,24 @@ riscv*) ;; esac + case "$vector" in + __riscv_vector) + case "$flen" in + 64) + float_machine=rvv + ;; + *) + # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only. + ;; + esac + ;; + *) + ;; + esac + + { $as_echo "$as_me:${as_lineno-$LINENO}: vector $vector flen $flen float_machine $float_machine" >&5 +$as_echo "$as_me: vector $vector flen $flen float_machine $float_machine" >&6;} + case "$float_abi" in soft) abi_flen=0 diff --git a/sysdeps/riscv/preconfigure.ac b/sysdeps/riscv/preconfigure.ac index a5c30e0dbf..b6b8bb46e4 100644 --- a/sysdeps/riscv/preconfigure.ac +++ b/sysdeps/riscv/preconfigure.ac @@ -7,6 +7,7 @@ riscv*) flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'` float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'` atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2` + vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2` case "$xlen" in 64 | 32) @@ -32,6 +33,23 @@ riscv*) ;; esac + case "$vector" in + __riscv_vector) + case "$flen" in + 64) + float_machine=rvv + ;; + *) + # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only. + ;; + esac + ;; + *) + ;; + esac + + AC_MSG_NOTICE([vector $vector flen $flen float_machine $float_machine]) + case "$float_abi" in soft) abi_flen=0