[01/11] stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
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Commit Message
From: Fangrui Song <maskray@google.com>
An output constraint takes a lvalue. While GCC happily strips the
incorrect lvalue to rvalue conversion, Clang rejects the code by
default:
error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions
---
stdlib/longlong.h | 186 +++++++++++++++++++++++-----------------------
1 file changed, 93 insertions(+), 93 deletions(-)
Comments
On Fri, 28 Oct 2022, Adhemerval Zanella via Libc-alpha wrote:
> From: Fangrui Song <maskray@google.com>
>
> An output constraint takes a lvalue. While GCC happily strips the
> incorrect lvalue to rvalue conversion, Clang rejects the code by
> default:
We treat GCC as the upstream source of this file.
On 2022-10-28, Joseph Myers wrote:
>On Fri, 28 Oct 2022, Adhemerval Zanella via Libc-alpha wrote:
>
>> From: Fangrui Song <maskray@google.com>
>>
>> An output constraint takes a lvalue. While GCC happily strips the
>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>> default:
>
>We treat GCC as the upstream source of this file.
I tried gcc-patches in 2021-10
https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html
stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
If the GCC patch is not favored, the clang build will have to use -fheinous-gnu-extensions :(
On 28/10/22 18:32, Fangrui Song wrote:
> On 2022-10-28, Joseph Myers wrote:
>> On Fri, 28 Oct 2022, Adhemerval Zanella via Libc-alpha wrote:
>>
>>> From: Fangrui Song <maskray@google.com>
>>>
>>> An output constraint takes a lvalue. While GCC happily strips the
>>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>>> default:
>>
>> We treat GCC as the upstream source of this file.
>
> I tried gcc-patches in 2021-10
> https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html
> stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
>
> If the GCC patch is not favored, the clang build will have to use -fheinous-gnu-extensions :(
I recall this conversion, thanks for bring this up again. I don't have a strong
preference, using -fheinous-gnu-extensions might be an option. It would require
an additional configure check and add the flag on each file.
On 31/10/22 15:32, Adhemerval Zanella Netto wrote:
>
>
> On 28/10/22 18:32, Fangrui Song wrote:
>> On 2022-10-28, Joseph Myers wrote:
>>> On Fri, 28 Oct 2022, Adhemerval Zanella via Libc-alpha wrote:
>>>
>>>> From: Fangrui Song <maskray@google.com>
>>>>
>>>> An output constraint takes a lvalue. While GCC happily strips the
>>>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>>>> default:
>>>
>>> We treat GCC as the upstream source of this file.
>>
>> I tried gcc-patches in 2021-10
>> https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html
>> stdlib/longlong.h: Remove incorrect lvalue to rvalue conversion from asm output constraints
>>
>> If the GCC patch is not favored, the clang build will have to use -fheinous-gnu-extensions :(
>
> I recall this conversion, thanks for bring this up again. I don't have a strong
> preference, using -fheinous-gnu-extensions might be an option. It would require
> an additional configure check and add the flag on each file.
Using -fheinous-gnu-extensions does not seem to be a long-term solution,
clang accepts it but still throws an warning:
warning: invalid use of a cast in an inline asm context requiring an lvalue:
accepted due to -fheinous-gnu-extensions, but clang may remove support for
this in the future
And we do not have a -Wno-heinous-gnu-extensions to suppress it. But what really
worries me that eventually clang decides to remove it.
From gcc thread, it is unlikely that the cast would be removed since they provide
a diagnostic way. So I am open to suggestion on how to proceed.
One option would be to start provide proper static inline function, so we can
remove the cast; and adapt the glibc code to use it. However it would result in
a quite large patch, and it would need to modify multiple projects (gcc, gmp,
glibc at least).
Another option would be to check at configure time if cast in inline asm
context is supported and disable the cast if not.
I am inclined for the later.
On Tue, 1 Nov 2022, Adhemerval Zanella Netto wrote:
> Another option would be to check at configure time if cast in inline asm
> context is supported and disable the cast if not.
The file is meant to be taken verbatim (no local changes) from GCC. So
you're getting into generating a file in the build tree based on automated
substitutions into the source file from GCC there.
On 01/11/22 11:18, Joseph Myers wrote:
> On Tue, 1 Nov 2022, Adhemerval Zanella Netto wrote:
>
>> Another option would be to check at configure time if cast in inline asm
>> context is supported and disable the cast if not.
>
> The file is meant to be taken verbatim (no local changes) from GCC. So
> you're getting into generating a file in the build tree based on automated
> substitutions into the source file from GCC there.
>
I am open to suggestions in fact, I am not sure if this option would be best
one. The automated substitution tends to be error prone with simple regex,
but it might the best option (specially because longlong.h is not an constant
updated file and the ABI won't change anytime soon).
On Fri, Oct 28, 2022 at 10:36 AM Adhemerval Zanella via Libc-alpha
<libc-alpha@sourceware.org> wrote:
>
> From: Fangrui Song <maskray@google.com>
>
> An output constraint takes a lvalue. While GCC happily strips the
> incorrect lvalue to rvalue conversion, Clang rejects the code by
> default:
For GCC this is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=2803 .
I wrote about the ones in longlong.h (inside GCC sources) in comment
#11 back in 2004 when I tried to fix GCC's front-end to reject this.
Thanks,
Andrew
>
> error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions
> ---
> stdlib/longlong.h | 186 +++++++++++++++++++++++-----------------------
> 1 file changed, 93 insertions(+), 93 deletions(-)
>
> diff --git a/stdlib/longlong.h b/stdlib/longlong.h
> index d8f76a43b5..303cc4e8d0 100644
> --- a/stdlib/longlong.h
> +++ b/stdlib/longlong.h
> @@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
> #if defined (__arc__) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%r" ((USItype) (ah)), \
> "rICal" ((USItype) (bh)), \
> "%r" ((USItype) (al)), \
> @@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
> : "cc")
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "r" ((USItype) (ah)), \
> "rICal" ((USItype) (bh)), \
> "r" ((USItype) (al)), \
> @@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
> && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%r" ((USItype) (ah)), \
> "rI" ((USItype) (bh)), \
> "%r" ((USItype) (al)), \
> "rI" ((USItype) (bl)) __CLOBBER_CC)
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "r" ((USItype) (ah)), \
> "rI" ((USItype) (bh)), \
> "r" ((USItype) (al)), \
> @@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
> " addcs %0, %0, #65536\n" \
> " adds %1, %1, %3, lsl #16\n" \
> " adc %0, %0, %3, lsr #16" \
> - : "=&r" ((USItype) (xh)), \
> - "=r" ((USItype) (xl)), \
> + : "=&r" (xh), \
> + "=r" (xl), \
> "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
> : "r" ((USItype) (a)), \
> "r" ((USItype) (b)) __CLOBBER_CC ); \
> @@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__hppa) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%rM" ((USItype) (ah)), \
> "rM" ((USItype) (bh)), \
> "%rM" ((USItype) (al)), \
> "rM" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "rM" ((USItype) (ah)), \
> "rM" ((USItype) (bh)), \
> "rM" ((USItype) (al)), \
> @@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%0" ((USItype) (ah)), \
> "g" ((USItype) (bh)), \
> "%1" ((USItype) (al)), \
> "g" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "0" ((USItype) (ah)), \
> "g" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> "g" ((USItype) (bl)))
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ("mul{l} %3" \
> - : "=a" ((USItype) (w0)), \
> - "=d" ((USItype) (w1)) \
> + : "=a" (w0), \
> + "=d" (w1) \
> : "%0" ((USItype) (u)), \
> "rm" ((USItype) (v)))
> #define udiv_qrnnd(q, r, n1, n0, dv) \
> __asm__ ("div{l} %4" \
> - : "=a" ((USItype) (q)), \
> - "=d" ((USItype) (r)) \
> + : "=a" (q), \
> + "=d" (r) \
> : "0" ((USItype) (n0)), \
> "1" ((USItype) (n1)), \
> "rm" ((USItype) (dv)))
> @@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__x86_64__) && W_TYPE_SIZE == 64
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
> - : "=r" ((UDItype) (sh)), \
> - "=&r" ((UDItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%0" ((UDItype) (ah)), \
> "rme" ((UDItype) (bh)), \
> "%1" ((UDItype) (al)), \
> "rme" ((UDItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
> - : "=r" ((UDItype) (sh)), \
> - "=&r" ((UDItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "0" ((UDItype) (ah)), \
> "rme" ((UDItype) (bh)), \
> "1" ((UDItype) (al)), \
> "rme" ((UDItype) (bl)))
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ("mul{q} %3" \
> - : "=a" ((UDItype) (w0)), \
> - "=d" ((UDItype) (w1)) \
> + : "=a" (w0), \
> + "=d" (w1) \
> : "%0" ((UDItype) (u)), \
> "rm" ((UDItype) (v)))
> #define udiv_qrnnd(q, r, n1, n0, dv) \
> __asm__ ("div{q} %4" \
> - : "=a" ((UDItype) (q)), \
> - "=d" ((UDItype) (r)) \
> + : "=a" (q), \
> + "=d" (r) \
> : "0" ((UDItype) (n0)), \
> "1" ((UDItype) (n1)), \
> "rm" ((UDItype) (dv)))
> @@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> /* The cmp clears the condition bit. */ \
> __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "0" ((USItype) (ah)), \
> "r" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> @@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> /* The cmp clears the condition bit. */ \
> __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "0" ((USItype) (ah)), \
> "r" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> @@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__mc68000__) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
> - : "=d" ((USItype) (sh)), \
> - "=&d" ((USItype) (sl)) \
> + : "=d" (sh), \
> + "=&d" (sl) \
> : "%0" ((USItype) (ah)), \
> "d" ((USItype) (bh)), \
> "%1" ((USItype) (al)), \
> "g" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
> - : "=d" ((USItype) (sh)), \
> - "=&d" ((USItype) (sl)) \
> + : "=d" (sh), \
> + "=&d" (sl) \
> : "0" ((USItype) (ah)), \
> "d" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> @@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if (defined (__mc68020__) && !defined (__mc68060__))
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ("mulu%.l %3,%1:%0" \
> - : "=d" ((USItype) (w0)), \
> - "=d" ((USItype) (w1)) \
> + : "=d" (w0), \
> + "=d" (w1) \
> : "%0" ((USItype) (u)), \
> "dmi" ((USItype) (v)))
> #define UMUL_TIME 45
> #define udiv_qrnnd(q, r, n1, n0, d) \
> __asm__ ("divu%.l %4,%1:%0" \
> - : "=d" ((USItype) (q)), \
> - "=d" ((USItype) (r)) \
> + : "=d" (q), \
> + "=d" (r) \
> : "0" ((USItype) (n0)), \
> "1" ((USItype) (n1)), \
> "dmi" ((USItype) (d)))
> #define UDIV_TIME 90
> #define sdiv_qrnnd(q, r, n1, n0, d) \
> __asm__ ("divs%.l %4,%1:%0" \
> - : "=d" ((USItype) (q)), \
> - "=d" ((USItype) (r)) \
> + : "=d" (q), \
> + "=d" (r) \
> : "0" ((USItype) (n0)), \
> "1" ((USItype) (n1)), \
> "dmi" ((USItype) (d)))
> @@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " move%.l %/d2,%1\n" \
> " add%.l %/d1,%/d0\n" \
> " move%.l %/d0,%0" \
> - : "=g" ((USItype) (xh)), \
> - "=g" ((USItype) (xl)) \
> + : "=g" (xh), \
> + "=g" (xl) \
> : "g" ((USItype) (a)), \
> "g" ((USItype) (b)) \
> : "d0", "d1", "d2", "d3", "d4")
> @@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " move%.l %/d2,%1\n" \
> " add%.l %/d1,%/d0\n" \
> " move%.l %/d0,%0" \
> - : "=g" ((USItype) (xh)), \
> - "=g" ((USItype) (xl)) \
> + : "=g" (xh)), \
> + "=g" (xl) \
> : "g" ((USItype) (a)), \
> "g" ((USItype) (b)) \
> : "d0", "d1", "d2", "d3", "d4")
> @@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__mc68020__) && !defined (__mcpu32__)
> #define count_leading_zeros(count, x) \
> __asm__ ("bfffo %1{%b2:%b2},%0" \
> - : "=d" ((USItype) (count)) \
> + : "=d" (count) \
> : "od" ((USItype) (x)), "n" (0))
> /* Some ColdFire architectures have a ff1 instruction supported via
> __builtin_clz. */
> @@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__m88000__) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%rJ" ((USItype) (ah)), \
> "rJ" ((USItype) (bh)), \
> "%rJ" ((USItype) (al)), \
> "rJ" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "rJ" ((USItype) (ah)), \
> "rJ" ((USItype) (bh)), \
> "rJ" ((USItype) (al)), \
> @@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("a %1,%5\n\tae %0,%3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%0" ((USItype) (ah)), \
> "r" ((USItype) (bh)), \
> "%1" ((USItype) (al)), \
> "r" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("s %1,%5\n\tse %0,%3" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "0" ((USItype) (ah)), \
> "r" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> @@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " m r2,%3\n" \
> " cas %0,r2,r0\n" \
> " mfs r10,%1" \
> - : "=r" ((USItype) (ph)), \
> - "=r" ((USItype) (pl)) \
> + : "=r" (ph), \
> + "=r" (pl) \
> : "%r" (__m0), \
> "r" (__m1) \
> : "r2"); \
> @@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
> do { \
> if ((x) >= 0x10000) \
> __asm__ ("clz %0,%1" \
> - : "=r" ((USItype) (count)) \
> + : "=r" (count) \
> : "r" ((USItype) (x) >> 16)); \
> else \
> { \
> __asm__ ("clz %0,%1" \
> - : "=r" ((USItype) (count)) \
> + : "=r" (count) \
> : "r" ((USItype) (x))); \
> (count) += 16; \
> } \
> @@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ( \
> "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
> - : "=r<" ((USItype)(w1)), \
> - "=r<" ((USItype)(w0)) \
> + : "=r<" (w1), \
> + "=r<" (w0) \
> : "r" ((USItype)(u)), \
> "r" ((USItype)(v)) \
> : "macl", "mach")
> @@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "%rJ" ((USItype) (ah)), \
> "rI" ((USItype) (bh)), \
> "%rJ" ((USItype) (al)), \
> @@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> __CLOBBER_CC)
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
> - : "=r" ((USItype) (sh)), \
> - "=&r" ((USItype) (sl)) \
> + : "=r" (sh), \
> + "=&r" (sl) \
> : "rJ" ((USItype) (ah)), \
> "rI" ((USItype) (bh)), \
> "rJ" ((USItype) (al)), \
> @@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
> register USItype __g1 asm ("g1"); \
> __asm__ ("umul\t%2,%3,%1\n\t" \
> "srlx\t%1, 32, %0" \
> - : "=r" ((USItype) (w1)), \
> + : "=r" (w1), \
> "=r" (__g1) \
> : "r" ((USItype) (u)), \
> "r" ((USItype) (v))); \
> @@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> "udiv\t%3,%4,%0\n\t" \
> "umul\t%0,%4,%1\n\t" \
> "sub\t%3,%1,%1" \
> - : "=&r" ((USItype) (__q)), \
> - "=&r" ((USItype) (__r)) \
> + : "=&r" (__q), \
> + "=&r" (__r) \
> : "r" ((USItype) (__n1)), \
> "r" ((USItype) (__n0)), \
> "r" ((USItype) (__d)))
> @@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__sparc_v8__)
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
> - : "=r" ((USItype) (w1)), \
> - "=r" ((USItype) (w0)) \
> + : "=r" (w1), \
> + "=r" (w0) \
> : "r" ((USItype) (u)), \
> "r" ((USItype) (v)))
> #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
> __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
> - : "=&r" ((USItype) (__q)), \
> - "=&r" ((USItype) (__r)) \
> + : "=&r" (__q), \
> + "=&r" (__r) \
> : "r" ((USItype) (__n1)), \
> "r" ((USItype) (__n0)), \
> "r" ((USItype) (__d)))
> @@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> instructions scan (ffs from high bit) and divscc. */
> #define umul_ppmm(w1, w0, u, v) \
> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
> - : "=r" ((USItype) (w1)), \
> - "=r" ((USItype) (w0)) \
> + : "=r" (w1), \
> + "=r" (w0) \
> : "r" ((USItype) (u)), \
> "r" ((USItype) (v)))
> #define udiv_qrnnd(q, r, n1, n0, d) \
> @@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " bl,a 1f\n" \
> " add %1,%4,%1\n" \
> "1: ! End of inline udiv_qrnnd" \
> - : "=r" ((USItype) (q)), \
> - "=r" ((USItype) (r)) \
> + : "=r" (q), \
> + "=r" (r) \
> : "r" ((USItype) (n1)), \
> "r" ((USItype) (n0)), \
> "rI" ((USItype) (d)) \
> @@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #define count_leading_zeros(count, x) \
> do { \
> __asm__ ("scan %1,1,%0" \
> - : "=r" ((USItype) (count)) \
> + : "=r" (count) \
> : "r" ((USItype) (x))); \
> } while (0)
> /* Early sparclites return 63 for an argument of 0, but they warn that future
> @@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " mulscc %%g1,0,%%g1\n" \
> " add %%g1,%%o5,%0\n" \
> " rd %%y,%1" \
> - : "=r" ((USItype) (w1)), \
> - "=r" ((USItype) (w0)) \
> + : "=r" (w1), \
> + "=r" (w0) \
> : "%rI" ((USItype) (u)), \
> "r" ((USItype) (v)) \
> : "g1", "o5" __AND_CLOBBER_CC)
> @@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> " sub %1,%2,%1\n" \
> "3: xnor %0,0,%0\n" \
> " ! End of inline udiv_qrnnd" \
> - : "=&r" ((USItype) (__q)), \
> - "=&r" ((USItype) (__r)) \
> + : "=&r" (__q), \
> + "=&r" (__r) \
> : "r" ((USItype) (__d)), \
> "1" ((USItype) (__n1)), \
> "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
> @@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> "add\t%r3,%4,%0\n\t" \
> "movcs\t%%xcc, 1, %2\n\t" \
> "add\t%0, %2, %0" \
> - : "=r" ((UDItype)(sh)), \
> - "=&r" ((UDItype)(sl)), \
> + : "=r" (sh), \
> + "=&r" (sl), \
> "+r" (__carry) \
> : "%rJ" ((UDItype)(ah)), \
> "rI" ((UDItype)(bh)), \
> @@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> "sub\t%r3,%4,%0\n\t" \
> "movcs\t%%xcc, 1, %2\n\t" \
> "sub\t%0, %2, %0" \
> - : "=r" ((UDItype)(sh)), \
> - "=&r" ((UDItype)(sl)), \
> + : "=r" (sh), \
> + "=&r" (sl), \
> "+r" (__carry) \
> : "%rJ" ((UDItype)(ah)), \
> "rI" ((UDItype)(bh)), \
> @@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
> "sllx %3,32,%3\n\t" \
> "add %1,%3,%1\n\t" \
> "add %5,%2,%0" \
> - : "=r" ((UDItype)(wh)), \
> - "=&r" ((UDItype)(wl)), \
> + : "=r" (wh), \
> + "=&r" (wl), \
> "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
> : "r" ((UDItype)(u)), \
> "r" ((UDItype)(v)) \
> @@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
> #if defined (__vax__) && W_TYPE_SIZE == 32
> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
> __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
> - : "=g" ((USItype) (sh)), \
> - "=&g" ((USItype) (sl)) \
> + : "=g" (sh)), \
> + "=&g" (sl) \
> : "%0" ((USItype) (ah)), \
> "g" ((USItype) (bh)), \
> "%1" ((USItype) (al)), \
> "g" ((USItype) (bl)))
> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
> __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
> - : "=g" ((USItype) (sh)), \
> - "=&g" ((USItype) (sl)) \
> + : "=g" (sh)), \
> + "=&g" (sl) \
> : "0" ((USItype) (ah)), \
> "g" ((USItype) (bh)), \
> "1" ((USItype) (al)), \
> --
> 2.34.1
>
On Tue, Nov 1, 2022 at 2:06 PM Adhemerval Zanella Netto via Libc-alpha
<libc-alpha@sourceware.org> wrote:
> I am open to suggestions in fact,
What about just using the compiler builtins directly and not using
this header at all?
On 02/11/22 12:14, Cristian Rodríguez wrote:
> On Tue, Nov 1, 2022 at 2:06 PM Adhemerval Zanella Netto via Libc-alpha
> <libc-alpha@sourceware.org> wrote:
>
>> I am open to suggestions in fact,
>
> What about just using the compiler builtins directly and not using
> this header at all?
My understanding is this header should be used in the scenario where the
builtin might generate libcalls, for instance on libgcc and/or libc.
On Wed, Nov 2, 2022 at 2:10 PM Adhemerval Zanella Netto
<adhemerval.zanella@linaro.org> wrote:
>
>
>
> On 02/11/22 12:14, Cristian Rodríguez wrote:
> > On Tue, Nov 1, 2022 at 2:06 PM Adhemerval Zanella Netto via Libc-alpha
> > <libc-alpha@sourceware.org> wrote:
> >
> >> I am open to suggestions in fact,
> >
> > What about just using the compiler builtins directly and not using
> > this header at all?
>
> My understanding is this header should be used in the scenario where the
> builtin might generate libcalls, for instance on libgcc and/or libc.
My - I confess very limited - research the other day suggests there
are very few targets without __clz* __ctz__ patterns.. On this case it
will indeed call libgcc (is that frowned upon still?) but not libc ...
On 02/11/22 16:43, Cristian Rodríguez wrote:
> On Wed, Nov 2, 2022 at 2:10 PM Adhemerval Zanella Netto
> <adhemerval.zanella@linaro.org> wrote:
>>
>>
>>
>> On 02/11/22 12:14, Cristian Rodríguez wrote:
>>> On Tue, Nov 1, 2022 at 2:06 PM Adhemerval Zanella Netto via Libc-alpha
>>> <libc-alpha@sourceware.org> wrote:
>>>
>>>> I am open to suggestions in fact,
>>>
>>> What about just using the compiler builtins directly and not using
>>> this header at all?
>>
>> My understanding is this header should be used in the scenario where the
>> builtin might generate libcalls, for instance on libgcc and/or libc.
>
> My - I confess very limited - research the other day suggests there
> are very few targets without __clz* __ctz__ patterns.. On this case it
> will indeed call libgcc (is that frowned upon still?) but not libc ...
This header is also quite ancient, I think it provided the counter leading
and trailing zero even before the ctz/clz builtins and before ffs libc function.
But I agree with you that builtins should be used when possible.
Another issue is the ctz/clz analogous is not the only interface it provides,
but also a some macros used extensively on some soft-fp routines. We will
also need to rewrite a lot of interfaces, which is shared with gcc as well.
On 2022-11-01, Andrew Pinski via Libc-alpha wrote:
> On Fri, Oct 28, 2022 at 10:36 AM Adhemerval Zanella via Libc-alpha
><libc-alpha@sourceware.org> wrote:
>>
>> From: Fangrui Song <maskray@google.com>
>>
>> An output constraint takes a lvalue. While GCC happily strips the
>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>> default:
>
>For GCC this is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=2803 .
>I wrote about the ones in longlong.h (inside GCC sources) in comment
>#11 back in 2004 when I tried to fix GCC's front-end to reject this.
>
>Thanks,
>Andrew
Thanks for the comment. Would GCC side consider
https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html ?
If GCC takes the patch to its diverged GMP 2.0 copy (released 1996), glibc can import the change.
>
>
>>
>> error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions
>> ---
>> stdlib/longlong.h | 186 +++++++++++++++++++++++-----------------------
>> 1 file changed, 93 insertions(+), 93 deletions(-)
>>
>> diff --git a/stdlib/longlong.h b/stdlib/longlong.h
>> index d8f76a43b5..303cc4e8d0 100644
>> --- a/stdlib/longlong.h
>> +++ b/stdlib/longlong.h
>> @@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> #if defined (__arc__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%r" ((USItype) (ah)), \
>> "rICal" ((USItype) (bh)), \
>> "%r" ((USItype) (al)), \
>> @@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> : "cc")
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "r" ((USItype) (ah)), \
>> "rICal" ((USItype) (bh)), \
>> "r" ((USItype) (al)), \
>> @@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%r" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "%r" ((USItype) (al)), \
>> "rI" ((USItype) (bl)) __CLOBBER_CC)
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "r" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "r" ((USItype) (al)), \
>> @@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> " addcs %0, %0, #65536\n" \
>> " adds %1, %1, %3, lsl #16\n" \
>> " adc %0, %0, %3, lsr #16" \
>> - : "=&r" ((USItype) (xh)), \
>> - "=r" ((USItype) (xl)), \
>> + : "=&r" (xh), \
>> + "=r" (xl), \
>> "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
>> : "r" ((USItype) (a)), \
>> "r" ((USItype) (b)) __CLOBBER_CC ); \
>> @@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__hppa) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rM" ((USItype) (ah)), \
>> "rM" ((USItype) (bh)), \
>> "%rM" ((USItype) (al)), \
>> "rM" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rM" ((USItype) (ah)), \
>> "rM" ((USItype) (bh)), \
>> "rM" ((USItype) (al)), \
>> @@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mul{l} %3" \
>> - : "=a" ((USItype) (w0)), \
>> - "=d" ((USItype) (w1)) \
>> + : "=a" (w0), \
>> + "=d" (w1) \
>> : "%0" ((USItype) (u)), \
>> "rm" ((USItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, dv) \
>> __asm__ ("div{l} %4" \
>> - : "=a" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=a" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "rm" ((USItype) (dv)))
>> @@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__x86_64__) && W_TYPE_SIZE == 64
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
>> - : "=r" ((UDItype) (sh)), \
>> - "=&r" ((UDItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((UDItype) (ah)), \
>> "rme" ((UDItype) (bh)), \
>> "%1" ((UDItype) (al)), \
>> "rme" ((UDItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
>> - : "=r" ((UDItype) (sh)), \
>> - "=&r" ((UDItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((UDItype) (ah)), \
>> "rme" ((UDItype) (bh)), \
>> "1" ((UDItype) (al)), \
>> "rme" ((UDItype) (bl)))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mul{q} %3" \
>> - : "=a" ((UDItype) (w0)), \
>> - "=d" ((UDItype) (w1)) \
>> + : "=a" (w0), \
>> + "=d" (w1) \
>> : "%0" ((UDItype) (u)), \
>> "rm" ((UDItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, dv) \
>> __asm__ ("div{q} %4" \
>> - : "=a" ((UDItype) (q)), \
>> - "=d" ((UDItype) (r)) \
>> + : "=a" (q), \
>> + "=d" (r) \
>> : "0" ((UDItype) (n0)), \
>> "1" ((UDItype) (n1)), \
>> "rm" ((UDItype) (dv)))
>> @@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> /* The cmp clears the condition bit. */ \
>> __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> /* The cmp clears the condition bit. */ \
>> __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__mc68000__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
>> - : "=d" ((USItype) (sh)), \
>> - "=&d" ((USItype) (sl)) \
>> + : "=d" (sh), \
>> + "=&d" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "d" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
>> - : "=d" ((USItype) (sh)), \
>> - "=&d" ((USItype) (sl)) \
>> + : "=d" (sh), \
>> + "=&d" (sl) \
>> : "0" ((USItype) (ah)), \
>> "d" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if (defined (__mc68020__) && !defined (__mc68060__))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mulu%.l %3,%1:%0" \
>> - : "=d" ((USItype) (w0)), \
>> - "=d" ((USItype) (w1)) \
>> + : "=d" (w0), \
>> + "=d" (w1) \
>> : "%0" ((USItype) (u)), \
>> "dmi" ((USItype) (v)))
>> #define UMUL_TIME 45
>> #define udiv_qrnnd(q, r, n1, n0, d) \
>> __asm__ ("divu%.l %4,%1:%0" \
>> - : "=d" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=d" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "dmi" ((USItype) (d)))
>> #define UDIV_TIME 90
>> #define sdiv_qrnnd(q, r, n1, n0, d) \
>> __asm__ ("divs%.l %4,%1:%0" \
>> - : "=d" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=d" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "dmi" ((USItype) (d)))
>> @@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " move%.l %/d2,%1\n" \
>> " add%.l %/d1,%/d0\n" \
>> " move%.l %/d0,%0" \
>> - : "=g" ((USItype) (xh)), \
>> - "=g" ((USItype) (xl)) \
>> + : "=g" (xh), \
>> + "=g" (xl) \
>> : "g" ((USItype) (a)), \
>> "g" ((USItype) (b)) \
>> : "d0", "d1", "d2", "d3", "d4")
>> @@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " move%.l %/d2,%1\n" \
>> " add%.l %/d1,%/d0\n" \
>> " move%.l %/d0,%0" \
>> - : "=g" ((USItype) (xh)), \
>> - "=g" ((USItype) (xl)) \
>> + : "=g" (xh)), \
>> + "=g" (xl) \
>> : "g" ((USItype) (a)), \
>> "g" ((USItype) (b)) \
>> : "d0", "d1", "d2", "d3", "d4")
>> @@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__mc68020__) && !defined (__mcpu32__)
>> #define count_leading_zeros(count, x) \
>> __asm__ ("bfffo %1{%b2:%b2},%0" \
>> - : "=d" ((USItype) (count)) \
>> + : "=d" (count) \
>> : "od" ((USItype) (x)), "n" (0))
>> /* Some ColdFire architectures have a ff1 instruction supported via
>> __builtin_clz. */
>> @@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__m88000__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rJ" ((USItype) (ah)), \
>> "rJ" ((USItype) (bh)), \
>> "%rJ" ((USItype) (al)), \
>> "rJ" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rJ" ((USItype) (ah)), \
>> "rJ" ((USItype) (bh)), \
>> "rJ" ((USItype) (al)), \
>> @@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("a %1,%5\n\tae %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "r" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("s %1,%5\n\tse %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " m r2,%3\n" \
>> " cas %0,r2,r0\n" \
>> " mfs r10,%1" \
>> - : "=r" ((USItype) (ph)), \
>> - "=r" ((USItype) (pl)) \
>> + : "=r" (ph), \
>> + "=r" (pl) \
>> : "%r" (__m0), \
>> "r" (__m1) \
>> : "r2"); \
>> @@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> do { \
>> if ((x) >= 0x10000) \
>> __asm__ ("clz %0,%1" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x) >> 16)); \
>> else \
>> { \
>> __asm__ ("clz %0,%1" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x))); \
>> (count) += 16; \
>> } \
>> @@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ( \
>> "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
>> - : "=r<" ((USItype)(w1)), \
>> - "=r<" ((USItype)(w0)) \
>> + : "=r<" (w1), \
>> + "=r<" (w0) \
>> : "r" ((USItype)(u)), \
>> "r" ((USItype)(v)) \
>> : "macl", "mach")
>> @@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rJ" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "%rJ" ((USItype) (al)), \
>> @@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> __CLOBBER_CC)
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rJ" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "rJ" ((USItype) (al)), \
>> @@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> register USItype __g1 asm ("g1"); \
>> __asm__ ("umul\t%2,%3,%1\n\t" \
>> "srlx\t%1, 32, %0" \
>> - : "=r" ((USItype) (w1)), \
>> + : "=r" (w1), \
>> "=r" (__g1) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v))); \
>> @@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "udiv\t%3,%4,%0\n\t" \
>> "umul\t%0,%4,%1\n\t" \
>> "sub\t%3,%1,%1" \
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__n1)), \
>> "r" ((USItype) (__n0)), \
>> "r" ((USItype) (__d)))
>> @@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__sparc_v8__)
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v)))
>> #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
>> __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__n1)), \
>> "r" ((USItype) (__n0)), \
>> "r" ((USItype) (__d)))
>> @@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> instructions scan (ffs from high bit) and divscc. */
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, d) \
>> @@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " bl,a 1f\n" \
>> " add %1,%4,%1\n" \
>> "1: ! End of inline udiv_qrnnd" \
>> - : "=r" ((USItype) (q)), \
>> - "=r" ((USItype) (r)) \
>> + : "=r" (q), \
>> + "=r" (r) \
>> : "r" ((USItype) (n1)), \
>> "r" ((USItype) (n0)), \
>> "rI" ((USItype) (d)) \
>> @@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define count_leading_zeros(count, x) \
>> do { \
>> __asm__ ("scan %1,1,%0" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x))); \
>> } while (0)
>> /* Early sparclites return 63 for an argument of 0, but they warn that future
>> @@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " mulscc %%g1,0,%%g1\n" \
>> " add %%g1,%%o5,%0\n" \
>> " rd %%y,%1" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "%rI" ((USItype) (u)), \
>> "r" ((USItype) (v)) \
>> : "g1", "o5" __AND_CLOBBER_CC)
>> @@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " sub %1,%2,%1\n" \
>> "3: xnor %0,0,%0\n" \
>> " ! End of inline udiv_qrnnd" \
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__d)), \
>> "1" ((USItype) (__n1)), \
>> "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
>> @@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "add\t%r3,%4,%0\n\t" \
>> "movcs\t%%xcc, 1, %2\n\t" \
>> "add\t%0, %2, %0" \
>> - : "=r" ((UDItype)(sh)), \
>> - "=&r" ((UDItype)(sl)), \
>> + : "=r" (sh), \
>> + "=&r" (sl), \
>> "+r" (__carry) \
>> : "%rJ" ((UDItype)(ah)), \
>> "rI" ((UDItype)(bh)), \
>> @@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "sub\t%r3,%4,%0\n\t" \
>> "movcs\t%%xcc, 1, %2\n\t" \
>> "sub\t%0, %2, %0" \
>> - : "=r" ((UDItype)(sh)), \
>> - "=&r" ((UDItype)(sl)), \
>> + : "=r" (sh), \
>> + "=&r" (sl), \
>> "+r" (__carry) \
>> : "%rJ" ((UDItype)(ah)), \
>> "rI" ((UDItype)(bh)), \
>> @@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "sllx %3,32,%3\n\t" \
>> "add %1,%3,%1\n\t" \
>> "add %5,%2,%0" \
>> - : "=r" ((UDItype)(wh)), \
>> - "=&r" ((UDItype)(wl)), \
>> + : "=r" (wh), \
>> + "=&r" (wl), \
>> "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
>> : "r" ((UDItype)(u)), \
>> "r" ((UDItype)(v)) \
>> @@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__vax__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
>> - : "=g" ((USItype) (sh)), \
>> - "=&g" ((USItype) (sl)) \
>> + : "=g" (sh)), \
>> + "=&g" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
>> - : "=g" ((USItype) (sh)), \
>> - "=&g" ((USItype) (sl)) \
>> + : "=g" (sh)), \
>> + "=&g" (sl) \
>> : "0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> --
>> 2.34.1
>>
[Fixing email address.. Really sorry for my mistake.]
On 2022-11-01, Andrew Pinski via Libc-alpha wrote:
> On Fri, Oct 28, 2022 at 10:36 AM Adhemerval Zanella via Libc-alpha
><libc-alpha@sourceware.org> wrote:
>>
>> From: Fangrui Song <maskray@google.com>
>>
>> An output constraint takes a lvalue. While GCC happily strips the
>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>> default:
>
>For GCC this is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=2803 .
>I wrote about the ones in longlong.h (inside GCC sources) in comment
>#11 back in 2004 when I tried to fix GCC's front-end to reject this.
>
>Thanks,
>Andrew
Thanks for the comment. Would GCC side consider
https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html ?
If GCC takes the patch to its diverged GMP 2.0 copy (released 1996), glibc can import the change.
>
>
>>
>> error: invalid use of a cast in a inline asm context requiring an lvalue: remove the cast or build with -fheinous-gnu-extensions
>> ---
>> stdlib/longlong.h | 186 +++++++++++++++++++++++-----------------------
>> 1 file changed, 93 insertions(+), 93 deletions(-)
>>
>> diff --git a/stdlib/longlong.h b/stdlib/longlong.h
>> index d8f76a43b5..303cc4e8d0 100644
>> --- a/stdlib/longlong.h
>> +++ b/stdlib/longlong.h
>> @@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> #if defined (__arc__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%r" ((USItype) (ah)), \
>> "rICal" ((USItype) (bh)), \
>> "%r" ((USItype) (al)), \
>> @@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> : "cc")
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "r" ((USItype) (ah)), \
>> "rICal" ((USItype) (bh)), \
>> "r" ((USItype) (al)), \
>> @@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%r" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "%r" ((USItype) (al)), \
>> "rI" ((USItype) (bl)) __CLOBBER_CC)
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "r" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "r" ((USItype) (al)), \
>> @@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
>> " addcs %0, %0, #65536\n" \
>> " adds %1, %1, %3, lsl #16\n" \
>> " adc %0, %0, %3, lsr #16" \
>> - : "=&r" ((USItype) (xh)), \
>> - "=r" ((USItype) (xl)), \
>> + : "=&r" (xh), \
>> + "=r" (xl), \
>> "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
>> : "r" ((USItype) (a)), \
>> "r" ((USItype) (b)) __CLOBBER_CC ); \
>> @@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__hppa) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rM" ((USItype) (ah)), \
>> "rM" ((USItype) (bh)), \
>> "%rM" ((USItype) (al)), \
>> "rM" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rM" ((USItype) (ah)), \
>> "rM" ((USItype) (bh)), \
>> "rM" ((USItype) (al)), \
>> @@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mul{l} %3" \
>> - : "=a" ((USItype) (w0)), \
>> - "=d" ((USItype) (w1)) \
>> + : "=a" (w0), \
>> + "=d" (w1) \
>> : "%0" ((USItype) (u)), \
>> "rm" ((USItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, dv) \
>> __asm__ ("div{l} %4" \
>> - : "=a" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=a" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "rm" ((USItype) (dv)))
>> @@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__x86_64__) && W_TYPE_SIZE == 64
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
>> - : "=r" ((UDItype) (sh)), \
>> - "=&r" ((UDItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((UDItype) (ah)), \
>> "rme" ((UDItype) (bh)), \
>> "%1" ((UDItype) (al)), \
>> "rme" ((UDItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
>> - : "=r" ((UDItype) (sh)), \
>> - "=&r" ((UDItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((UDItype) (ah)), \
>> "rme" ((UDItype) (bh)), \
>> "1" ((UDItype) (al)), \
>> "rme" ((UDItype) (bl)))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mul{q} %3" \
>> - : "=a" ((UDItype) (w0)), \
>> - "=d" ((UDItype) (w1)) \
>> + : "=a" (w0), \
>> + "=d" (w1) \
>> : "%0" ((UDItype) (u)), \
>> "rm" ((UDItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, dv) \
>> __asm__ ("div{q} %4" \
>> - : "=a" ((UDItype) (q)), \
>> - "=d" ((UDItype) (r)) \
>> + : "=a" (q), \
>> + "=d" (r) \
>> : "0" ((UDItype) (n0)), \
>> "1" ((UDItype) (n1)), \
>> "rm" ((UDItype) (dv)))
>> @@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> /* The cmp clears the condition bit. */ \
>> __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> /* The cmp clears the condition bit. */ \
>> __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__mc68000__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
>> - : "=d" ((USItype) (sh)), \
>> - "=&d" ((USItype) (sl)) \
>> + : "=d" (sh), \
>> + "=&d" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "d" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
>> - : "=d" ((USItype) (sh)), \
>> - "=&d" ((USItype) (sl)) \
>> + : "=d" (sh), \
>> + "=&d" (sl) \
>> : "0" ((USItype) (ah)), \
>> "d" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if (defined (__mc68020__) && !defined (__mc68060__))
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("mulu%.l %3,%1:%0" \
>> - : "=d" ((USItype) (w0)), \
>> - "=d" ((USItype) (w1)) \
>> + : "=d" (w0), \
>> + "=d" (w1) \
>> : "%0" ((USItype) (u)), \
>> "dmi" ((USItype) (v)))
>> #define UMUL_TIME 45
>> #define udiv_qrnnd(q, r, n1, n0, d) \
>> __asm__ ("divu%.l %4,%1:%0" \
>> - : "=d" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=d" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "dmi" ((USItype) (d)))
>> #define UDIV_TIME 90
>> #define sdiv_qrnnd(q, r, n1, n0, d) \
>> __asm__ ("divs%.l %4,%1:%0" \
>> - : "=d" ((USItype) (q)), \
>> - "=d" ((USItype) (r)) \
>> + : "=d" (q), \
>> + "=d" (r) \
>> : "0" ((USItype) (n0)), \
>> "1" ((USItype) (n1)), \
>> "dmi" ((USItype) (d)))
>> @@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " move%.l %/d2,%1\n" \
>> " add%.l %/d1,%/d0\n" \
>> " move%.l %/d0,%0" \
>> - : "=g" ((USItype) (xh)), \
>> - "=g" ((USItype) (xl)) \
>> + : "=g" (xh), \
>> + "=g" (xl) \
>> : "g" ((USItype) (a)), \
>> "g" ((USItype) (b)) \
>> : "d0", "d1", "d2", "d3", "d4")
>> @@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " move%.l %/d2,%1\n" \
>> " add%.l %/d1,%/d0\n" \
>> " move%.l %/d0,%0" \
>> - : "=g" ((USItype) (xh)), \
>> - "=g" ((USItype) (xl)) \
>> + : "=g" (xh)), \
>> + "=g" (xl) \
>> : "g" ((USItype) (a)), \
>> "g" ((USItype) (b)) \
>> : "d0", "d1", "d2", "d3", "d4")
>> @@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__mc68020__) && !defined (__mcpu32__)
>> #define count_leading_zeros(count, x) \
>> __asm__ ("bfffo %1{%b2:%b2},%0" \
>> - : "=d" ((USItype) (count)) \
>> + : "=d" (count) \
>> : "od" ((USItype) (x)), "n" (0))
>> /* Some ColdFire architectures have a ff1 instruction supported via
>> __builtin_clz. */
>> @@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__m88000__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rJ" ((USItype) (ah)), \
>> "rJ" ((USItype) (bh)), \
>> "%rJ" ((USItype) (al)), \
>> "rJ" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rJ" ((USItype) (ah)), \
>> "rJ" ((USItype) (bh)), \
>> "rJ" ((USItype) (al)), \
>> @@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("a %1,%5\n\tae %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "r" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("s %1,%5\n\tse %0,%3" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "0" ((USItype) (ah)), \
>> "r" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> @@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " m r2,%3\n" \
>> " cas %0,r2,r0\n" \
>> " mfs r10,%1" \
>> - : "=r" ((USItype) (ph)), \
>> - "=r" ((USItype) (pl)) \
>> + : "=r" (ph), \
>> + "=r" (pl) \
>> : "%r" (__m0), \
>> "r" (__m1) \
>> : "r2"); \
>> @@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> do { \
>> if ((x) >= 0x10000) \
>> __asm__ ("clz %0,%1" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x) >> 16)); \
>> else \
>> { \
>> __asm__ ("clz %0,%1" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x))); \
>> (count) += 16; \
>> } \
>> @@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ( \
>> "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
>> - : "=r<" ((USItype)(w1)), \
>> - "=r<" ((USItype)(w0)) \
>> + : "=r<" (w1), \
>> + "=r<" (w0) \
>> : "r" ((USItype)(u)), \
>> "r" ((USItype)(v)) \
>> : "macl", "mach")
>> @@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "%rJ" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "%rJ" ((USItype) (al)), \
>> @@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> __CLOBBER_CC)
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
>> - : "=r" ((USItype) (sh)), \
>> - "=&r" ((USItype) (sl)) \
>> + : "=r" (sh), \
>> + "=&r" (sl) \
>> : "rJ" ((USItype) (ah)), \
>> "rI" ((USItype) (bh)), \
>> "rJ" ((USItype) (al)), \
>> @@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> register USItype __g1 asm ("g1"); \
>> __asm__ ("umul\t%2,%3,%1\n\t" \
>> "srlx\t%1, 32, %0" \
>> - : "=r" ((USItype) (w1)), \
>> + : "=r" (w1), \
>> "=r" (__g1) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v))); \
>> @@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "udiv\t%3,%4,%0\n\t" \
>> "umul\t%0,%4,%1\n\t" \
>> "sub\t%3,%1,%1" \
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__n1)), \
>> "r" ((USItype) (__n0)), \
>> "r" ((USItype) (__d)))
>> @@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__sparc_v8__)
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v)))
>> #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
>> __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__n1)), \
>> "r" ((USItype) (__n0)), \
>> "r" ((USItype) (__d)))
>> @@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> instructions scan (ffs from high bit) and divscc. */
>> #define umul_ppmm(w1, w0, u, v) \
>> __asm__ ("umul %2,%3,%1;rd %%y,%0" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "r" ((USItype) (u)), \
>> "r" ((USItype) (v)))
>> #define udiv_qrnnd(q, r, n1, n0, d) \
>> @@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " bl,a 1f\n" \
>> " add %1,%4,%1\n" \
>> "1: ! End of inline udiv_qrnnd" \
>> - : "=r" ((USItype) (q)), \
>> - "=r" ((USItype) (r)) \
>> + : "=r" (q), \
>> + "=r" (r) \
>> : "r" ((USItype) (n1)), \
>> "r" ((USItype) (n0)), \
>> "rI" ((USItype) (d)) \
>> @@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #define count_leading_zeros(count, x) \
>> do { \
>> __asm__ ("scan %1,1,%0" \
>> - : "=r" ((USItype) (count)) \
>> + : "=r" (count) \
>> : "r" ((USItype) (x))); \
>> } while (0)
>> /* Early sparclites return 63 for an argument of 0, but they warn that future
>> @@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " mulscc %%g1,0,%%g1\n" \
>> " add %%g1,%%o5,%0\n" \
>> " rd %%y,%1" \
>> - : "=r" ((USItype) (w1)), \
>> - "=r" ((USItype) (w0)) \
>> + : "=r" (w1), \
>> + "=r" (w0) \
>> : "%rI" ((USItype) (u)), \
>> "r" ((USItype) (v)) \
>> : "g1", "o5" __AND_CLOBBER_CC)
>> @@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> " sub %1,%2,%1\n" \
>> "3: xnor %0,0,%0\n" \
>> " ! End of inline udiv_qrnnd" \
>> - : "=&r" ((USItype) (__q)), \
>> - "=&r" ((USItype) (__r)) \
>> + : "=&r" (__q), \
>> + "=&r" (__r) \
>> : "r" ((USItype) (__d)), \
>> "1" ((USItype) (__n1)), \
>> "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
>> @@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "add\t%r3,%4,%0\n\t" \
>> "movcs\t%%xcc, 1, %2\n\t" \
>> "add\t%0, %2, %0" \
>> - : "=r" ((UDItype)(sh)), \
>> - "=&r" ((UDItype)(sl)), \
>> + : "=r" (sh), \
>> + "=&r" (sl), \
>> "+r" (__carry) \
>> : "%rJ" ((UDItype)(ah)), \
>> "rI" ((UDItype)(bh)), \
>> @@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "sub\t%r3,%4,%0\n\t" \
>> "movcs\t%%xcc, 1, %2\n\t" \
>> "sub\t%0, %2, %0" \
>> - : "=r" ((UDItype)(sh)), \
>> - "=&r" ((UDItype)(sl)), \
>> + : "=r" (sh), \
>> + "=&r" (sl), \
>> "+r" (__carry) \
>> : "%rJ" ((UDItype)(ah)), \
>> "rI" ((UDItype)(bh)), \
>> @@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> "sllx %3,32,%3\n\t" \
>> "add %1,%3,%1\n\t" \
>> "add %5,%2,%0" \
>> - : "=r" ((UDItype)(wh)), \
>> - "=&r" ((UDItype)(wl)), \
>> + : "=r" (wh), \
>> + "=&r" (wl), \
>> "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
>> : "r" ((UDItype)(u)), \
>> "r" ((UDItype)(v)) \
>> @@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
>> #if defined (__vax__) && W_TYPE_SIZE == 32
>> #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
>> __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
>> - : "=g" ((USItype) (sh)), \
>> - "=&g" ((USItype) (sl)) \
>> + : "=g" (sh)), \
>> + "=&g" (sl) \
>> : "%0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "%1" ((USItype) (al)), \
>> "g" ((USItype) (bl)))
>> #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
>> __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
>> - : "=g" ((USItype) (sh)), \
>> - "=&g" ((USItype) (sl)) \
>> + : "=g" (sh)), \
>> + "=&g" (sl) \
>> : "0" ((USItype) (ah)), \
>> "g" ((USItype) (bh)), \
>> "1" ((USItype) (al)), \
>> --
>> 2.34.1
>>
On 06/11/22 16:32, Fangrui Song wrote:
> [Fixing email address.. Really sorry for my mistake.]
>
> On 2022-11-01, Andrew Pinski via Libc-alpha wrote:
>> On Fri, Oct 28, 2022 at 10:36 AM Adhemerval Zanella via Libc-alpha
>> <libc-alpha@sourceware.org> wrote:
>>>
>>> From: Fangrui Song <maskray@google.com>
>>>
>>> An output constraint takes a lvalue. While GCC happily strips the
>>> incorrect lvalue to rvalue conversion, Clang rejects the code by
>>> default:
>>
>> For GCC this is https://gcc.gnu.org/bugzilla/show_bug.cgi?id=2803 .
>> I wrote about the ones in longlong.h (inside GCC sources) in comment
>> #11 back in 2004 when I tried to fix GCC's front-end to reject this.
>>
>> Thanks,
>> Andrew
>
> Thanks for the comment. Would GCC side consider
> https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581722.html ?
> If GCC takes the patch to its diverged GMP 2.0 copy (released 1996), glibc can import the change.
It would make the glibc changes way easier to maintain, since I really
dislike the hack I proposed to fix on glibc side [1] (which I don't
see how to fix it without rewriting a lot of stuff to avoid the use
of longlong.h).
[1] https://patchwork.sourceware.org/project/glibc/patch/20221102145559.1962008-4-adhemerval.zanella@linaro.org/
@@ -194,8 +194,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
#if defined (__arc__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%r" ((USItype) (ah)), \
"rICal" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
@@ -203,8 +203,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
: "cc")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "r" ((USItype) (ah)), \
"rICal" ((USItype) (bh)), \
"r" ((USItype) (al)), \
@@ -230,16 +230,16 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
&& W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%r" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
"rI" ((USItype) (bl)) __CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "r" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"r" ((USItype) (al)), \
@@ -262,8 +262,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
" addcs %0, %0, #65536\n" \
" adds %1, %1, %3, lsl #16\n" \
" adc %0, %0, %3, lsr #16" \
- : "=&r" ((USItype) (xh)), \
- "=r" ((USItype) (xl)), \
+ : "=&r" (xh), \
+ "=r" (xl), \
"=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
: "r" ((USItype) (a)), \
"r" ((USItype) (b)) __CLOBBER_CC ); \
@@ -348,16 +348,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__hppa) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rM" ((USItype) (ah)), \
"rM" ((USItype) (bh)), \
"%rM" ((USItype) (al)), \
"rM" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rM" ((USItype) (ah)), \
"rM" ((USItype) (bh)), \
"rM" ((USItype) (al)), \
@@ -456,30 +456,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mul{l} %3" \
- : "=a" ((USItype) (w0)), \
- "=d" ((USItype) (w1)) \
+ : "=a" (w0), \
+ "=d" (w1) \
: "%0" ((USItype) (u)), \
"rm" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, dv) \
__asm__ ("div{l} %4" \
- : "=a" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
+ : "=a" (q), \
+ "=d" (r) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"rm" ((USItype) (dv)))
@@ -492,30 +492,30 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__x86_64__) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((UDItype) (ah)), \
"rme" ((UDItype) (bh)), \
"%1" ((UDItype) (al)), \
"rme" ((UDItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
- : "=r" ((UDItype) (sh)), \
- "=&r" ((UDItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((UDItype) (ah)), \
"rme" ((UDItype) (bh)), \
"1" ((UDItype) (al)), \
"rme" ((UDItype) (bl)))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mul{q} %3" \
- : "=a" ((UDItype) (w0)), \
- "=d" ((UDItype) (w1)) \
+ : "=a" (w0), \
+ "=d" (w1) \
: "%0" ((UDItype) (u)), \
"rm" ((UDItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, dv) \
__asm__ ("div{q} %4" \
- : "=a" ((UDItype) (q)), \
- "=d" ((UDItype) (r)) \
+ : "=a" (q), \
+ "=d" (r) \
: "0" ((UDItype) (n0)), \
"1" ((UDItype) (n1)), \
"rm" ((UDItype) (dv)))
@@ -609,8 +609,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
@@ -619,8 +619,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
@@ -631,16 +631,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__mc68000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
- : "=d" ((USItype) (sh)), \
- "=&d" ((USItype) (sl)) \
+ : "=d" (sh), \
+ "=&d" (sl) \
: "%0" ((USItype) (ah)), \
"d" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
- : "=d" ((USItype) (sh)), \
- "=&d" ((USItype) (sl)) \
+ : "=d" (sh), \
+ "=&d" (sl) \
: "0" ((USItype) (ah)), \
"d" ((USItype) (bh)), \
"1" ((USItype) (al)), \
@@ -650,23 +650,23 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if (defined (__mc68020__) && !defined (__mc68060__))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
- : "=d" ((USItype) (w0)), \
- "=d" ((USItype) (w1)) \
+ : "=d" (w0), \
+ "=d" (w1) \
: "%0" ((USItype) (u)), \
"dmi" ((USItype) (v)))
#define UMUL_TIME 45
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
- : "=d" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
+ : "=d" (q), \
+ "=d" (r) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"dmi" ((USItype) (d)))
#define UDIV_TIME 90
#define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
- : "=d" ((USItype) (q)), \
- "=d" ((USItype) (r)) \
+ : "=d" (q), \
+ "=d" (r) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"dmi" ((USItype) (d)))
@@ -700,8 +700,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" move%.l %/d2,%1\n" \
" add%.l %/d1,%/d0\n" \
" move%.l %/d0,%0" \
- : "=g" ((USItype) (xh)), \
- "=g" ((USItype) (xl)) \
+ : "=g" (xh), \
+ "=g" (xl) \
: "g" ((USItype) (a)), \
"g" ((USItype) (b)) \
: "d0", "d1", "d2", "d3", "d4")
@@ -736,8 +736,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" move%.l %/d2,%1\n" \
" add%.l %/d1,%/d0\n" \
" move%.l %/d0,%0" \
- : "=g" ((USItype) (xh)), \
- "=g" ((USItype) (xl)) \
+ : "=g" (xh)), \
+ "=g" (xl) \
: "g" ((USItype) (a)), \
"g" ((USItype) (b)) \
: "d0", "d1", "d2", "d3", "d4")
@@ -751,7 +751,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__mc68020__) && !defined (__mcpu32__)
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
- : "=d" ((USItype) (count)) \
+ : "=d" (count) \
: "od" ((USItype) (x)), "n" (0))
/* Some ColdFire architectures have a ff1 instruction supported via
__builtin_clz. */
@@ -764,16 +764,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__m88000__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rJ" ((USItype) (ah)), \
"rJ" ((USItype) (bh)), \
"%rJ" ((USItype) (al)), \
"rJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rJ" ((USItype) (ah)), \
"rJ" ((USItype) (bh)), \
"rJ" ((USItype) (al)), \
@@ -1000,16 +1000,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5\n\tae %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"r" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5\n\tse %0,%3" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
@@ -1038,8 +1038,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" m r2,%3\n" \
" cas %0,r2,r0\n" \
" mfs r10,%1" \
- : "=r" ((USItype) (ph)), \
- "=r" ((USItype) (pl)) \
+ : "=r" (ph), \
+ "=r" (pl) \
: "%r" (__m0), \
"r" (__m1) \
: "r2"); \
@@ -1052,12 +1052,12 @@ extern UDItype __umulsidi3 (USItype, USItype);
do { \
if ((x) >= 0x10000) \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype) (count)) \
+ : "=r" (count) \
: "r" ((USItype) (x) >> 16)); \
else \
{ \
__asm__ ("clz %0,%1" \
- : "=r" ((USItype) (count)) \
+ : "=r" (count) \
: "r" ((USItype) (x))); \
(count) += 16; \
} \
@@ -1119,8 +1119,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
#define umul_ppmm(w1, w0, u, v) \
__asm__ ( \
"dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
- : "=r<" ((USItype)(w1)), \
- "=r<" ((USItype)(w0)) \
+ : "=r<" (w1), \
+ "=r<" (w0) \
: "r" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "macl", "mach")
@@ -1191,8 +1191,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
&& W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "%rJ" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"%rJ" ((USItype) (al)), \
@@ -1200,8 +1200,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
__CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
- : "=r" ((USItype) (sh)), \
- "=&r" ((USItype) (sl)) \
+ : "=r" (sh), \
+ "=&r" (sl) \
: "rJ" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"rJ" ((USItype) (al)), \
@@ -1213,7 +1213,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
register USItype __g1 asm ("g1"); \
__asm__ ("umul\t%2,%3,%1\n\t" \
"srlx\t%1, 32, %0" \
- : "=r" ((USItype) (w1)), \
+ : "=r" (w1), \
"=r" (__g1) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v))); \
@@ -1224,8 +1224,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
"udiv\t%3,%4,%0\n\t" \
"umul\t%0,%4,%1\n\t" \
"sub\t%3,%1,%1" \
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
+ : "=&r" (__q), \
+ "=&r" (__r) \
: "r" ((USItype) (__n1)), \
"r" ((USItype) (__n0)), \
"r" ((USItype) (__d)))
@@ -1233,14 +1233,14 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__sparc_v8__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v)))
#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
__asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
+ : "=&r" (__q), \
+ "=&r" (__r) \
: "r" ((USItype) (__n1)), \
"r" ((USItype) (__n0)), \
"r" ((USItype) (__d)))
@@ -1250,8 +1250,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
instructions scan (ffs from high bit) and divscc. */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, d) \
@@ -1294,8 +1294,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" bl,a 1f\n" \
" add %1,%4,%1\n" \
"1: ! End of inline udiv_qrnnd" \
- : "=r" ((USItype) (q)), \
- "=r" ((USItype) (r)) \
+ : "=r" (q), \
+ "=r" (r) \
: "r" ((USItype) (n1)), \
"r" ((USItype) (n0)), \
"rI" ((USItype) (d)) \
@@ -1304,7 +1304,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
#define count_leading_zeros(count, x) \
do { \
__asm__ ("scan %1,1,%0" \
- : "=r" ((USItype) (count)) \
+ : "=r" (count) \
: "r" ((USItype) (x))); \
} while (0)
/* Early sparclites return 63 for an argument of 0, but they warn that future
@@ -1354,8 +1354,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" mulscc %%g1,0,%%g1\n" \
" add %%g1,%%o5,%0\n" \
" rd %%y,%1" \
- : "=r" ((USItype) (w1)), \
- "=r" ((USItype) (w0)) \
+ : "=r" (w1), \
+ "=r" (w0) \
: "%rI" ((USItype) (u)), \
"r" ((USItype) (v)) \
: "g1", "o5" __AND_CLOBBER_CC)
@@ -1387,8 +1387,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
" sub %1,%2,%1\n" \
"3: xnor %0,0,%0\n" \
" ! End of inline udiv_qrnnd" \
- : "=&r" ((USItype) (__q)), \
- "=&r" ((USItype) (__r)) \
+ : "=&r" (__q), \
+ "=&r" (__r) \
: "r" ((USItype) (__d)), \
"1" ((USItype) (__n1)), \
"0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
@@ -1407,8 +1407,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
"add\t%r3,%4,%0\n\t" \
"movcs\t%%xcc, 1, %2\n\t" \
"add\t%0, %2, %0" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)), \
+ : "=r" (sh), \
+ "=&r" (sl), \
"+r" (__carry) \
: "%rJ" ((UDItype)(ah)), \
"rI" ((UDItype)(bh)), \
@@ -1424,8 +1424,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
"sub\t%r3,%4,%0\n\t" \
"movcs\t%%xcc, 1, %2\n\t" \
"sub\t%0, %2, %0" \
- : "=r" ((UDItype)(sh)), \
- "=&r" ((UDItype)(sl)), \
+ : "=r" (sh), \
+ "=&r" (sl), \
"+r" (__carry) \
: "%rJ" ((UDItype)(ah)), \
"rI" ((UDItype)(bh)), \
@@ -1459,8 +1459,8 @@ extern UDItype __umulsidi3 (USItype, USItype);
"sllx %3,32,%3\n\t" \
"add %1,%3,%1\n\t" \
"add %5,%2,%0" \
- : "=r" ((UDItype)(wh)), \
- "=&r" ((UDItype)(wl)), \
+ : "=r" (wh), \
+ "=&r" (wl), \
"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
: "r" ((UDItype)(u)), \
"r" ((UDItype)(v)) \
@@ -1473,16 +1473,16 @@ extern UDItype __umulsidi3 (USItype, USItype);
#if defined (__vax__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
+ : "=g" (sh)), \
+ "=&g" (sl) \
: "%0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
- : "=g" ((USItype) (sh)), \
- "=&g" ((USItype) (sl)) \
+ : "=g" (sh)), \
+ "=&g" (sl) \
: "0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"1" ((USItype) (al)), \