From patchwork Mon Jul 18 10:38:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 56114 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F05FF3852749 for ; Mon, 18 Jul 2022 10:38:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F05FF3852749 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1658140719; bh=u2BC+GHAX8JRUYAAZlTeZ7IVTxmbt7L2CzzHEH76m5M=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=Ua4JFZF9+2LZrO3H++34NG6TDeGGsnRKkh7QVMj81h+xrxn02W4DNtyobFMjrOViS hpfRVkpyxRpTLDu+ickvpqtBjEb4mQfEWHtPmUSjNA993v1yf7WhJ22M9I4lBUzwPB AwfO6HSNerCEFBCBARKI23XmDifrvMZpZCvBnuwI= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by sourceware.org (Postfix) with ESMTPS id 9DB213857404 for ; Mon, 18 Jul 2022 10:38:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9DB213857404 Received: by mail-pf1-x430.google.com with SMTP id e16so10208184pfm.11 for ; Mon, 18 Jul 2022 03:38:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=u2BC+GHAX8JRUYAAZlTeZ7IVTxmbt7L2CzzHEH76m5M=; b=mAn9HhkEnQjMGVHhlYrv+J5DAIYob3QK/DXENfILD6IJlZc7rM9xVJEfvyba/SuX7l 08q5uwx1wLHMdDWrZUEavLNQATL3rc+26cgysKfAtD1hTeG+rr8UYJU4CJ7txo+pQ/dk 8d7tCnX36GKdcLU1LURMdjeVtcS0VlFpn4mGFrxChKbafho1R39hHYhCMhGBVvh9Y8YB tSAy/gsJO607bbF+x/fpKu5+kcBbR08EZgLjN7Qb8hfK/VIqjRlLjXTqkNvWoCUxUDRA 0mlqAAbogcSYmtpYH0wR+99lYAZKtn1M1lB5fUReAUxk/ehty2r69syhDZlRIYqDKSgL shCQ== X-Gm-Message-State: AJIora/lcCN3BZdoIbiabA7TEH/vDk4vcryrnwEfiUMQWoDfAoOXSG7h tGCMm/YS4u4T5VRiLmoTR1K5Wz1S5eqfWw== X-Google-Smtp-Source: AGRyM1s+7znCU3q9WXKJAAWILt5hb+cCJn/hC6b3TSVmsyomhv7ErNqkMYCp8D6/m3vCfOa2tMKg9g== X-Received: by 2002:a05:6a00:1386:b0:52a:d5f9:2837 with SMTP id t6-20020a056a00138600b0052ad5f92837mr28094158pfg.5.1658140696403; Mon, 18 Jul 2022 03:38:16 -0700 (PDT) Received: from noah-tgl.. ([210.177.125.238]) by smtp.gmail.com with ESMTPSA id n10-20020a170902e54a00b00161e50e2245sm9151442plf.178.2022.07.18.03.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 03:38:15 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v1] x86: Fix type of `Slow_SSE4_2` def in isa-level.h Date: Mon, 18 Jul 2022 03:38:10 -0700 Message-Id: <20220718103811.1842054-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_ABUSEAT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Change from `Slow_SSE42_X86_ISA_LEVEL` to `Slow_SSE4_2_X86_ISA_LEVEL`. Currently the def is unused to no need to change anything else. --- sysdeps/x86/isa-level.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index 3c4480aba7..fe56af7e2b 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -104,7 +104,7 @@ /* NB: This feature is disable when ISA level >= 3. All CPUs with this feature don't run on glibc built with ISA level >= 3. */ -#define Slow_SSE42_X86_ISA_LEVEL 3 +#define Slow_SSE4_2_X86_ISA_LEVEL 3 /* Feature(s) enabled when ISA level >= 2. */ #define Fast_Unaligned_Load_X86_ISA_LEVEL 2