From patchwork Tue Jun 28 04:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55467 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A13C03852743 for ; Tue, 28 Jun 2022 04:07:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A13C03852743 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656389248; bh=O4FQV4h+GGlv6gy+FnLQJ7cxdKbpCv6QXnhWSTS1mbk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=rrdFjeXQv4BmopRTUPuFrLD9WwRg1GVfpE8QxcTuN3rx2BSjhrsjScpPEp49nbtcj PPsUkJCW3m8sQ+qeKU+XPfwTPhHz/IC/68bMrJ5QdZipz2m3xKMhQvoXi5JJC9SAA+ zOkxFyIn3K3qe4agkyBZwrjFSkQjVn3reW8vV8UU= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by sourceware.org (Postfix) with ESMTPS id 8D92B385AE75 for ; Tue, 28 Jun 2022 04:07:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8D92B385AE75 Received: by mail-pj1-x1032.google.com with SMTP id l2so10168823pjf.1 for ; Mon, 27 Jun 2022 21:07:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O4FQV4h+GGlv6gy+FnLQJ7cxdKbpCv6QXnhWSTS1mbk=; b=x2DBsBgTqTpevA37tCjMJ0b0RsHca3w3NWepGwBchcCZN8jCcqy/BkxmDOPLIpM58Q QRVeX0yvFarTj50/eBBa/VeaLEK0H56C1oW+RRFHjdAciTWL2p2jHKAoG9U7sUkWD9eg fcRoJhxvyTZYQ4FfYgTHQroyEsYlk/sH8XNpNRN5iIwjsGJ/SbCP0GW4jYwucZFdcZPw vIhMianTWvZrulNd4WZ+sYguvoZk44LSFrL6MAd/yC6rPfM6YD5PbNvGDndSR/9GDLgX L89HgJmBQHaDHgzOZ1eA+Z3gN2KX9QNK34UBxfzIT3L7hpbxLR+sjrzy4aNLeAvkhT+L a0ZA== X-Gm-Message-State: AJIora8svl7+Jbvqr/rOXJxN1xS5XnMbj6bF09/5hIqS8z3r2GfGUJr8 r6C3rmw8l3kpymesH3GWolCSOUqxbfY= X-Google-Smtp-Source: AGRyM1sERCwM2gCjpnw9KGgoJLKt5/TczTvcZwL4N7rzMmLjaJixwLG5z+inVRLjF3knoJ9Q8tq1Pg== X-Received: by 2002:a17:903:22c2:b0:16a:3039:adb1 with SMTP id y2-20020a17090322c200b0016a3039adb1mr1616542plg.28.1656389226134; Mon, 27 Jun 2022 21:07:06 -0700 (PDT) Received: from noah-tgl.. ([2600:1010:b016:fb15:ad7e:a465:b31a:6f06]) by smtp.gmail.com with ESMTPSA id a14-20020a1709027d8e00b0016b7ba73a18sm3119085plm.38.2022.06.27.21.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 21:07:05 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v5] x86: Add more feature definitions to isa-level.h Date: Mon, 27 Jun 2022 21:07:03 -0700 Message-Id: <20220628040703.2296390-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628010446.3464287-1-goldstein.w.n@gmail.com> References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit doesn't change anything in itself. It is just to add definitions that will be needed by future patches. --- sysdeps/x86/isa-level.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index f293aea906..77f9e2c0c3 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -67,15 +67,27 @@ /* Depending on the minimum ISA level, a feature check result can be a compile-time constant.. */ + +/* For CPU_FEATURE_USABLE_P. */ + /* ISA level >= 4 guaranteed includes. */ #define AVX512F_X86_ISA_LEVEL 4 #define AVX512VL_X86_ISA_LEVEL 4 #define AVX512BW_X86_ISA_LEVEL 4 +#define AVX512DQ_X86_ISA_LEVEL 4 /* ISA level >= 3 guaranteed includes. */ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 +#define MOVBE_X86_ISA_LEVEL 3 + +/* ISA level >= 2 guaranteed includes. */ +#define SSE4_2_X86_ISA_LEVEL 2 +#define SSSE3_X86_ISA_LEVEL 2 + + +/* For X86_ISA_CPU_FEATURES_ARCH_P. */ /* NB: This feature is enabled when ISA level >= 3, which was disabled for the following CPUs: @@ -89,6 +101,9 @@ when ISA level < 3. */ #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 +/* Feature(s) enabled when ISA level >= 2. */ +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 + /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P runtime checks. They differ in two ways.