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[73.231.94.136]) by smtp.gmail.com with ESMTPSA id 71-20020a63034a000000b0040d2d9f15e0sm756682pgd.20.2022.06.23.23.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jun 2022 23:37:58 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v1 4/7] x86: Add comment with ISA level for all targets support by GCC12.1 Date: Thu, 23 Jun 2022 23:36:51 -0700 Message-Id: <20220624063653.2126416-4-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220624063653.2126416-1-goldstein.w.n@gmail.com> References: <20220624063653.2126416-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This is just a quality of life change to make it easier to see how the ISA level will effect a given build. --- sysdeps/x86/isa-level.h | 67 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 2 deletions(-) diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index e1a30ed83e..f14ae5cc00 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -64,8 +64,71 @@ #define MINIMUM_X86_ISA_LEVEL \ (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4) - -/* +/* ISA levels for known GCC targets as of GCC12.1: + * + * amdfam10 -> 1 + * athlon-fx -> 1 + * athlon64 -> 1 + * athlon64-sse3 -> 1 + * atom -> 1 + * barcelona -> 1 + * bonnell -> 1 + * btver1 -> 1 + * core2 -> 1 + * eden-x2 -> 1 + * eden-x4 -> 1 + * k8 -> 1 + * k8-sse3 -> 1 + * nano -> 1 + * nano-1000 -> 1 + * nano-2000 -> 1 + * nano-3000 -> 1 + * nano-x2 -> 1 + * nano-x4 -> 1 + * nocona -> 1 + * opteron -> 1 + * opteron-sse3 -> 1 + * x86-64 -> 1 + * bdver1 -> 2 + * bdver2 -> 2 + * bdver3 -> 2 + * btver2 -> 2 + * core-avx-i -> 2 + * corei7 -> 2 + * corei7-avx -> 2 + * goldmont -> 2 + * goldmont-plus -> 2 + * ivybridge -> 2 + * nehalem -> 2 + * sandybridge -> 2 + * silvermont -> 2 + * slm -> 2 + * tremont -> 2 + * westmere -> 2 + * x86-64-v2 -> 2 + * alderlake -> 3 + * bdver4 -> 3 + * broadwell -> 3 + * core-avx2 -> 3 + * haswell -> 3 + * knl -> 3 + * knm -> 3 + * skylake -> 3 + * x86-64-v3 -> 3 + * znver1 -> 3 + * znver2 -> 3 + * znver3 -> 3 + * cannonlake -> 4 + * cascadelake -> 4 + * cooperlake -> 4 + * icelake-client -> 4 + * icelake-server -> 4 + * rocketlake -> 4 + * sapphirerapids -> 4 + * skylake-avx512 -> 4 + * tigerlake -> 4 + * x86-64-v4 -> 4 + * * CPU Features that are hard coded as enabled/disabled depending on * ISA build level. * - Values > 0 features are always ENABLED if: