From patchwork Mon Mar 7 15:01:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Pandey X-Patchwork-Id: 51737 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C4783857C5F for ; Mon, 7 Mar 2022 16:33:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6C4783857C5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1646670831; bh=Dev8aaPJNL0tnvw5ivwHCDBvtLVHvrh6p+sblMIdjUs=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=ot1A8HBwbvUIpz54SKbbaUd8KYVZYPscWU+FNtjFmTLv0gGUGEKc5xQrMd1N2d5OK tsfxJRZkARfzyd3mdbJ8w0Oar/S1lk4fFsoWnnmg9asIwjBTXyTwK2thtw9D3cNewH zn05pRWlXwvSxMH90yg9+TO0upyBzPOeJKCpV8VM= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 3E3583858003 for ; Mon, 7 Mar 2022 15:03:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3E3583858003 X-IronPort-AV: E=McAfee;i="6200,9189,10278"; a="235017283" X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="235017283" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2022 07:02:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,162,1643702400"; d="scan'208";a="595526501" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga008.fm.intel.com with ESMTP; 07 Mar 2022 07:02:10 -0800 Received: from gskx-1.sc.intel.com (gskx-1.sc.intel.com [172.25.149.211]) by scymds01.sc.intel.com with ESMTP id 227F21fI016772; Mon, 7 Mar 2022 07:02:10 -0800 To: libc-alpha@sourceware.org Subject: [PATCH 104/126] x86_64: Fix svml_s_log2f4_core_sse4.S code formatting Date: Mon, 7 Mar 2022 07:01:39 -0800 Message-Id: <20220307150201.10590-105-skpgkp2@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220307150201.10590-1-skpgkp2@gmail.com> References: <20220307150201.10590-1-skpgkp2@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FORGED_GMAIL_RCVD, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, HK_RANDOM_ENVFROM, HK_RANDOM_FROM, KAM_DMARC_NONE, KAM_DMARC_STATUS, NML_ADSP_CUSTOM_MED, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Sunil K Pandey via Libc-alpha From: Sunil Pandey Reply-To: Sunil K Pandey Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit contains following formatting changes 1. Instructions proceeded by a tab. 2. Instruction less than 8 characters in length have a tab between it and the first operand. 3. Instruction greater than 7 characters in length have a space between it and the first operand. 4. Tabs after `#define`d names and their value. 5. 8 space at the beginning of line replaced by tab. 6. Indent comments with code. 7. Remove redundent .text section. --- .../fpu/multiarch/svml_s_log2f4_core_sse4.S | 329 +++++++++--------- 1 file changed, 164 insertions(+), 165 deletions(-) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core_sse4.S b/sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core_sse4.S index 6d3de152a4..bc6a778b75 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core_sse4.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core_sse4.S @@ -29,195 +29,194 @@ /* Offsets for data table __svml_slog2_data_internal */ -#define MinNorm 0 -#define MaxNorm 16 -#define iBrkValue 32 -#define iOffExpoMask 48 -#define One 64 -#define sPoly 80 +#define MinNorm 0 +#define MaxNorm 16 +#define iBrkValue 32 +#define iOffExpoMask 48 +#define One 64 +#define sPoly 80 #include - .text - .section .text.sse4,"ax",@progbits + .section .text.sse4, "ax", @progbits ENTRY(_ZGVbN4v_log2f_sse4) - subq $72, %rsp - cfi_def_cfa_offset(80) - movaps %xmm0, %xmm1 - -/* reduction: compute r,n */ - movdqu iBrkValue+__svml_slog2_data_internal(%rip), %xmm2 - movaps %xmm0, %xmm4 - movdqu iOffExpoMask+__svml_slog2_data_internal(%rip), %xmm10 - psubd %xmm2, %xmm1 - pand %xmm1, %xmm10 - movaps %xmm0, %xmm3 - paddd %xmm2, %xmm10 - psrad $23, %xmm1 - movups sPoly+__svml_slog2_data_internal(%rip), %xmm5 - movups sPoly+32+__svml_slog2_data_internal(%rip), %xmm6 - movups sPoly+64+__svml_slog2_data_internal(%rip), %xmm7 - movups sPoly+96+__svml_slog2_data_internal(%rip), %xmm9 - cmpltps MinNorm+__svml_slog2_data_internal(%rip), %xmm4 - cmpnleps MaxNorm+__svml_slog2_data_internal(%rip), %xmm3 - cvtdq2ps %xmm1, %xmm1 - subps One+__svml_slog2_data_internal(%rip), %xmm10 - mulps %xmm10, %xmm5 - movaps %xmm10, %xmm8 - mulps %xmm10, %xmm6 - mulps %xmm10, %xmm8 - addps sPoly+16+__svml_slog2_data_internal(%rip), %xmm5 - mulps %xmm10, %xmm7 - addps sPoly+48+__svml_slog2_data_internal(%rip), %xmm6 - mulps %xmm10, %xmm9 - mulps %xmm8, %xmm5 - addps sPoly+80+__svml_slog2_data_internal(%rip), %xmm7 - addps sPoly+112+__svml_slog2_data_internal(%rip), %xmm9 - addps %xmm5, %xmm6 - mulps %xmm8, %xmm6 - orps %xmm3, %xmm4 - -/* combine and get argument value range mask */ - movmskps %xmm4, %edx - addps %xmm6, %xmm7 - mulps %xmm7, %xmm8 - addps %xmm8, %xmm9 - mulps %xmm10, %xmm9 - addps sPoly+128+__svml_slog2_data_internal(%rip), %xmm9 - mulps %xmm9, %xmm10 - addps %xmm10, %xmm1 - testl %edx, %edx - -/* Go to special inputs processing branch */ - jne L(SPECIAL_VALUES_BRANCH) - # LOE rbx rbp r12 r13 r14 r15 edx xmm0 xmm1 - -/* Restore registers - * and exit the function - */ + subq $72, %rsp + cfi_def_cfa_offset(80) + movaps %xmm0, %xmm1 + + /* reduction: compute r, n */ + movdqu iBrkValue+__svml_slog2_data_internal(%rip), %xmm2 + movaps %xmm0, %xmm4 + movdqu iOffExpoMask+__svml_slog2_data_internal(%rip), %xmm10 + psubd %xmm2, %xmm1 + pand %xmm1, %xmm10 + movaps %xmm0, %xmm3 + paddd %xmm2, %xmm10 + psrad $23, %xmm1 + movups sPoly+__svml_slog2_data_internal(%rip), %xmm5 + movups sPoly+32+__svml_slog2_data_internal(%rip), %xmm6 + movups sPoly+64+__svml_slog2_data_internal(%rip), %xmm7 + movups sPoly+96+__svml_slog2_data_internal(%rip), %xmm9 + cmpltps MinNorm+__svml_slog2_data_internal(%rip), %xmm4 + cmpnleps MaxNorm+__svml_slog2_data_internal(%rip), %xmm3 + cvtdq2ps %xmm1, %xmm1 + subps One+__svml_slog2_data_internal(%rip), %xmm10 + mulps %xmm10, %xmm5 + movaps %xmm10, %xmm8 + mulps %xmm10, %xmm6 + mulps %xmm10, %xmm8 + addps sPoly+16+__svml_slog2_data_internal(%rip), %xmm5 + mulps %xmm10, %xmm7 + addps sPoly+48+__svml_slog2_data_internal(%rip), %xmm6 + mulps %xmm10, %xmm9 + mulps %xmm8, %xmm5 + addps sPoly+80+__svml_slog2_data_internal(%rip), %xmm7 + addps sPoly+112+__svml_slog2_data_internal(%rip), %xmm9 + addps %xmm5, %xmm6 + mulps %xmm8, %xmm6 + orps %xmm3, %xmm4 + + /* combine and get argument value range mask */ + movmskps %xmm4, %edx + addps %xmm6, %xmm7 + mulps %xmm7, %xmm8 + addps %xmm8, %xmm9 + mulps %xmm10, %xmm9 + addps sPoly+128+__svml_slog2_data_internal(%rip), %xmm9 + mulps %xmm9, %xmm10 + addps %xmm10, %xmm1 + testl %edx, %edx + + /* Go to special inputs processing branch */ + jne L(SPECIAL_VALUES_BRANCH) + # LOE rbx rbp r12 r13 r14 r15 edx xmm0 xmm1 + + /* Restore registers + * and exit the function + */ L(EXIT): - movaps %xmm1, %xmm0 - addq $72, %rsp - cfi_def_cfa_offset(8) - ret - cfi_def_cfa_offset(80) - -/* Branch to process - * special inputs - */ + movaps %xmm1, %xmm0 + addq $72, %rsp + cfi_def_cfa_offset(8) + ret + cfi_def_cfa_offset(80) + + /* Branch to process + * special inputs + */ L(SPECIAL_VALUES_BRANCH): - movups %xmm0, 32(%rsp) - movups %xmm1, 48(%rsp) - # LOE rbx rbp r12 r13 r14 r15 edx - - xorl %eax, %eax - movq %r12, 16(%rsp) - cfi_offset(12, -64) - movl %eax, %r12d - movq %r13, 8(%rsp) - cfi_offset(13, -72) - movl %edx, %r13d - movq %r14, (%rsp) - cfi_offset(14, -80) - # LOE rbx rbp r15 r12d r13d - -/* Range mask - * bits check - */ + movups %xmm0, 32(%rsp) + movups %xmm1, 48(%rsp) + # LOE rbx rbp r12 r13 r14 r15 edx + + xorl %eax, %eax + movq %r12, 16(%rsp) + cfi_offset(12, -64) + movl %eax, %r12d + movq %r13, 8(%rsp) + cfi_offset(13, -72) + movl %edx, %r13d + movq %r14, (%rsp) + cfi_offset(14, -80) + # LOE rbx rbp r15 r12d r13d + + /* Range mask + * bits check + */ L(RANGEMASK_CHECK): - btl %r12d, %r13d + btl %r12d, %r13d -/* Call scalar math function */ - jc L(SCALAR_MATH_CALL) - # LOE rbx rbp r15 r12d r13d + /* Call scalar math function */ + jc L(SCALAR_MATH_CALL) + # LOE rbx rbp r15 r12d r13d -/* Special inputs - * processing loop - */ + /* Special inputs + * processing loop + */ L(SPECIAL_VALUES_LOOP): - incl %r12d - cmpl $4, %r12d - -/* Check bits in range mask */ - jl L(RANGEMASK_CHECK) - # LOE rbx rbp r15 r12d r13d - - movq 16(%rsp), %r12 - cfi_restore(12) - movq 8(%rsp), %r13 - cfi_restore(13) - movq (%rsp), %r14 - cfi_restore(14) - movups 48(%rsp), %xmm1 - -/* Go to exit */ - jmp L(EXIT) - cfi_offset(12, -64) - cfi_offset(13, -72) - cfi_offset(14, -80) - # LOE rbx rbp r12 r13 r14 r15 xmm1 - -/* Scalar math fucntion call - * to process special input - */ + incl %r12d + cmpl $4, %r12d + + /* Check bits in range mask */ + jl L(RANGEMASK_CHECK) + # LOE rbx rbp r15 r12d r13d + + movq 16(%rsp), %r12 + cfi_restore(12) + movq 8(%rsp), %r13 + cfi_restore(13) + movq (%rsp), %r14 + cfi_restore(14) + movups 48(%rsp), %xmm1 + + /* Go to exit */ + jmp L(EXIT) + cfi_offset(12, -64) + cfi_offset(13, -72) + cfi_offset(14, -80) + # LOE rbx rbp r12 r13 r14 r15 xmm1 + + /* Scalar math fucntion call + * to process special input + */ L(SCALAR_MATH_CALL): - movl %r12d, %r14d - movss 32(%rsp,%r14,4), %xmm0 - call log2f@PLT - # LOE rbx rbp r14 r15 r12d r13d xmm0 + movl %r12d, %r14d + movss 32(%rsp, %r14, 4), %xmm0 + call log2f@PLT + # LOE rbx rbp r14 r15 r12d r13d xmm0 - movss %xmm0, 48(%rsp,%r14,4) + movss %xmm0, 48(%rsp, %r14, 4) -/* Process special inputs in loop */ - jmp L(SPECIAL_VALUES_LOOP) - # LOE rbx rbp r15 r12d r13d + /* Process special inputs in loop */ + jmp L(SPECIAL_VALUES_LOOP) + # LOE rbx rbp r15 r12d r13d END(_ZGVbN4v_log2f_sse4) - .section .rodata, "a" - .align 16 + .section .rodata, "a" + .align 16 #ifdef __svml_slog2_data_internal_typedef typedef unsigned int VUINT32; typedef struct { - __declspec(align(16)) VUINT32 MinNorm[4][1]; - __declspec(align(16)) VUINT32 MaxNorm[4][1]; - __declspec(align(16)) VUINT32 iBrkValue[4][1]; - __declspec(align(16)) VUINT32 iOffExpoMask[4][1]; - __declspec(align(16)) VUINT32 One[4][1]; - __declspec(align(16)) VUINT32 sPoly[9][4][1]; + __declspec(align(16)) VUINT32 MinNorm[4][1]; + __declspec(align(16)) VUINT32 MaxNorm[4][1]; + __declspec(align(16)) VUINT32 iBrkValue[4][1]; + __declspec(align(16)) VUINT32 iOffExpoMask[4][1]; + __declspec(align(16)) VUINT32 One[4][1]; + __declspec(align(16)) VUINT32 sPoly[9][4][1]; } __svml_slog2_data_internal; #endif __svml_slog2_data_internal: - /*== MinNorm ==*/ - .long 0x00800000, 0x00800000, 0x00800000, 0x00800000 - /*== MaxNorm ==*/ - .align 16 - .long 0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff - /*== iBrkValue = SP 2/3 ==*/ - .align 16 - .long 0x3f2aaaab, 0x3f2aaaab, 0x3f2aaaab, 0x3f2aaaab - /*== iOffExpoMask = SP significand mask ==*/ - .align 16 - .long 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff - /*== sOne = SP 1.0 ==*/ - .align 16 - .long 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 - /*== spoly[9] ==*/ - .align 16 - .long 0x3e554012, 0x3e554012, 0x3e554012, 0x3e554012 /* coeff9 */ - .long 0xbe638E14, 0xbe638E14, 0xbe638E14, 0xbe638E14 /* coeff8 */ - .long 0x3e4D660B, 0x3e4D660B, 0x3e4D660B, 0x3e4D660B /* coeff7 */ - .long 0xbe727824, 0xbe727824, 0xbe727824, 0xbe727824 /* coeff6 */ - .long 0x3e93DD07, 0x3e93DD07, 0x3e93DD07, 0x3e93DD07 /* coeff5 */ - .long 0xbeB8B969, 0xbeB8B969, 0xbeB8B969, 0xbeB8B969 /* coeff4 */ - .long 0x3eF637C0, 0x3eF637C0, 0x3eF637C0, 0x3eF637C0 /* coeff3 */ - .long 0xbf38AA2B, 0xbf38AA2B, 0xbf38AA2B, 0xbf38AA2B /* coeff2 */ - .long 0x3fB8AA3B, 0x3fB8AA3B, 0x3fB8AA3B, 0x3fB8AA3B /* coeff1 */ - .align 16 - .type __svml_slog2_data_internal,@object - .size __svml_slog2_data_internal,.-__svml_slog2_data_internal + /* MinNorm */ + .long 0x00800000, 0x00800000, 0x00800000, 0x00800000 + /* MaxNorm */ + .align 16 + .long 0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff + /* iBrkValue = SP 2/3 */ + .align 16 + .long 0x3f2aaaab, 0x3f2aaaab, 0x3f2aaaab, 0x3f2aaaab + /* iOffExpoMask = SP significand mask */ + .align 16 + .long 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff + /* sOne = SP 1.0 */ + .align 16 + .long 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + /* spoly[9] */ + .align 16 + .long 0x3e554012, 0x3e554012, 0x3e554012, 0x3e554012 /* coeff9 */ + .long 0xbe638E14, 0xbe638E14, 0xbe638E14, 0xbe638E14 /* coeff8 */ + .long 0x3e4D660B, 0x3e4D660B, 0x3e4D660B, 0x3e4D660B /* coeff7 */ + .long 0xbe727824, 0xbe727824, 0xbe727824, 0xbe727824 /* coeff6 */ + .long 0x3e93DD07, 0x3e93DD07, 0x3e93DD07, 0x3e93DD07 /* coeff5 */ + .long 0xbeB8B969, 0xbeB8B969, 0xbeB8B969, 0xbeB8B969 /* coeff4 */ + .long 0x3eF637C0, 0x3eF637C0, 0x3eF637C0, 0x3eF637C0 /* coeff3 */ + .long 0xbf38AA2B, 0xbf38AA2B, 0xbf38AA2B, 0xbf38AA2B /* coeff2 */ + .long 0x3fB8AA3B, 0x3fB8AA3B, 0x3fB8AA3B, 0x3fB8AA3B /* coeff1 */ + .align 16 + .type __svml_slog2_data_internal, @object + .size __svml_slog2_data_internal, .-__svml_slog2_data_internal