diff mbox series

powerpc: Fix unrecognized instruction errors with recent GCC

Message ID 20210914181958.749314-1-pc@us.ibm.com
State New
Headers show
Series powerpc: Fix unrecognized instruction errors with recent GCC | expand

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent
dj/TryBot-32bit success Build for i686

Commit Message

Paul A. Clarke Sept. 14, 2021, 6:19 p.m. UTC
Recent versions of GCC stopped passing "-many" to the assembler,
so some instructions which were under older, more stringent
"machine" directives no longer compile with unrecognized instructions
in that context.

In tst-ucontext-ppc64-vscr.c, while the instructions provoking the new
error messages are bracketed by ".machine power5", which is ostensibly
Power ISA 2.03 (POWER5), the POWER5 processor did not support the
VSX subset, so these instructions are not recognized as "power5".

Error: unrecognized opcode: `vspltisb'
Error: unrecognized opcode: `vpkuwus'
Error: unrecognized opcode: `mfvscr'
Error: unrecognized opcode: `stvx'

Manually adding the VSX subset via ".machine altivec" is sufficient.
---
 sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
index 28c87fcef72b..d3fc4ab589f4 100644
--- a/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
+++ b/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c
@@ -50,6 +50,7 @@  do_test (void)
   /* Set SAT bit in VSCR register.  */
   asm volatile (".machine push;\n"
 		".machine \"power5\";\n"
+		".machine altivec;\n"
 		"vspltisb %0,0;\n"
 		"vspltisb %1,-1;\n"
 		"vpkuwus %0,%0,%1;\n"