From patchwork Tue Jul 20 20:57:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 44442 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39B86398AC2F for ; Tue, 20 Jul 2021 21:05:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39B86398AC2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1626815108; bh=odYQCC6fnDHMlbIJt9bomvs2aal4TG5WdXesBnaP1NY=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Sic4hswT8gm5ZOwz7rsnplcKqG9rQSnswAtxYTn23sxF6RCUqdfinx9MgNUTBkSkc mdcI/Tb3QRIt5VCdCVKmcdVbRL60V9fLxjIHsqliYD8sTWAAopmH5+F9W1Bqksi91h rOEGHcEHgBC9eFykjJ26lqMplGU2MdidEFaZCv5k= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from smtprelay-out1.synopsys.com (smtprelay-out1.synopsys.com [149.117.87.133]) by sourceware.org (Postfix) with ESMTPS id 68119398D404 for ; Tue, 20 Jul 2021 20:58:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 68119398D404 Received: from mailhost.synopsys.com (sv2-mailhost2.synopsys.com [10.205.2.134]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client CN "mailhost.synopsys.com", Issuer "SNPSica2" (verified OK)) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 8930BC3788; Tue, 20 Jul 2021 20:58:11 +0000 (UTC) Received: from vineetg-Latitude-7400.internal.synopsys.com (snps-fugpbdpduq.internal.synopsys.com [10.202.17.37]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client did not present a certificate) by mailhost.synopsys.com (Postfix) with ESMTPSA id 9E04EA0268; Tue, 20 Jul 2021 20:58:11 +0000 (UTC) X-SNPS-Relay: synopsys.com To: libc-alpha@sourceware.org Subject: [PATCH 1/2] ARC: fp: (micro)optimize FPU_STATUS read by eliding FWE bit clearing Date: Tue, 20 Jul 2021 13:57:59 -0700 Message-Id: <20210720205800.1056218-2-vgupta@synopsys.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720205800.1056218-1-vgupta@synopsys.com> References: <20210720205800.1056218-1-vgupta@synopsys.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Vineet Gupta via Libc-alpha From: Vineet Gupta Reply-To: Vineet Gupta Cc: Vineet Gupta , linux-snps-arc@lists.infradead.org Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Any FPU_STATUS write needs setting the FWE bit (31) whcih just provides a "control signal" to enable explicit write (vs. the side-effect of FPU instructions). However this bit is RAZ and write-only, thus effectively never stored in FPU_STATUS register. Thus when reading the register there is no need to clear it. This shaves off a BCLR instruction from the fe*exceptino family of functions and while no big deal still makes sense to do. This came up when debugging a race in math/test-fenv-tls [1] [1]: https://github.com/foss-for-synopsys-dwc-arc-processors/linux/issues/54 Signed-off-by: Vineet Gupta --- sysdeps/arc/fpu_control.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/sysdeps/arc/fpu_control.h b/sysdeps/arc/fpu_control.h index c7d101e7838f..ae4348321c16 100644 --- a/sysdeps/arc/fpu_control.h +++ b/sysdeps/arc/fpu_control.h @@ -81,21 +81,20 @@ typedef unsigned int fpu_control_t; # define _FPU_SETCW(cw) __asm__ volatile ("sr %0, [0x300]" : : "r" (cw)) /* Macros for accessing the hardware status word. - FWE bit is special as it controls if actual status bits could be wrritten - explicitly (other than FPU instructions). We handle it here to keep the - callers agnostic of it: - - clear it out when reporting status bits - - always set it when changing status bits. */ + Writing to FPU_STATUS requires a "control" bit FWE to be able to set the + exception flags directly (as opposed to side-effects of FP instructions). + That is done in the macro here to keeps callers agnostic of this detail. + And given FWE is write-only and RAZ, no need to "clear" it in _FPU_GETS + macro. */ # define _FPU_GETS(cw) \ __asm__ volatile ("lr %0, [0x301] \r\n" \ - "bclr %0, %0, 31 \r\n" \ : "=r" (cw)) # define _FPU_SETS(cw) \ do { \ - unsigned int __tmp = 0x80000000 | (cw); \ + unsigned int __fwe = 0x80000000 | (cw); \ __asm__ volatile ("sr %0, [0x301] \r\n" \ - : : "r" (__tmp)); \ + : : "r" (__fwe)); \ } while (0) /* Default control word set at startup. */