diff mbox series

[2/3] powerpc64: Check cacheline size before using optimised memset routines

Message ID 20210706105107.1866836-2-anton@ozlabs.org
State Changes Requested
Delegated to: Tulio Magno Quites Machado Filho
Headers show
Series [1/3] powerpc64: Replace some PPC_FEATURE_HAS_VSX with PPC_FEATURE_ARCH_2_06 | expand

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent

Commit Message

Anton Blanchard July 6, 2021, 10:51 a.m. UTC
A number of optimised memset routines assume the cacheline size is 128B,
so we better check before using them.
---
 sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

Comments

Tulio Magno Quites Machado Filho July 8, 2021, 10:33 p.m. UTC | #1
Anton Blanchard via Libc-alpha <libc-alpha@sourceware.org> writes:

> A number of optimised memset routines assume the cacheline size is 128B,
> so we better check before using them.

The code looks good to me, but it's missing the same tests for bzero().

It's also important to keep sysdeps/powerpc/powerpc64/multiarch/ifunc-impl-list.c
in sync with both functions.

Like what this patch does:
https://github.com/tuliom/glibc/commit/5b3f36c16d97db739ea5fd422d2230b4dddd2512
diff mbox series

Patch

diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c
index c1aa143f60..056e911699 100644
--- a/sysdeps/powerpc/powerpc64/multiarch/memset.c
+++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c
@@ -43,16 +43,21 @@  libc_ifunc (__libc_memset,
 # ifdef __LITTLE_ENDIAN__
 	    (hwcap2 & PPC_FEATURE2_ARCH_3_1
 	     && hwcap2 & PPC_FEATURE2_HAS_ISEL
-	     && hwcap & PPC_FEATURE_HAS_VSX)
+	     && hwcap & PPC_FEATURE_HAS_VSX
+	     && GLRO(dl_cache_line_size) == 128)
 	    ? __memset_power10 :
 # endif
-            (hwcap2 & PPC_FEATURE2_ARCH_2_07)
+            (hwcap2 & PPC_FEATURE2_ARCH_2_07
+	     && GLRO(dl_cache_line_size) == 128)
             ? __memset_power8 :
-	      (hwcap & PPC_FEATURE_ARCH_2_06)
+	      (hwcap & PPC_FEATURE_ARCH_2_06
+	       && GLRO(dl_cache_line_size) == 128)
 	      ? __memset_power7 :
-		(hwcap & PPC_FEATURE_ARCH_2_05)
+		(hwcap & PPC_FEATURE_ARCH_2_05
+	         && GLRO(dl_cache_line_size) == 128)
 		? __memset_power6 :
-		  (hwcap & PPC_FEATURE_POWER4)
+		  (hwcap & PPC_FEATURE_POWER4
+	           && GLRO(dl_cache_line_size) == 128)
 		  ? __memset_power4
             : __memset_ppc);