From patchwork Wed May 12 09:26:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naohiro Tamura X-Patchwork-Id: 43386 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 483743890410; Wed, 12 May 2021 09:27:50 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from esa10.hc1455-7.c3s2.iphmx.com (esa10.hc1455-7.c3s2.iphmx.com [139.138.36.225]) by sourceware.org (Postfix) with ESMTPS id 5AC483890410 for ; Wed, 12 May 2021 09:27:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5AC483890410 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=fujitsu.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=naohirot@fujitsu.com IronPort-SDR: pfGuECWfg6CECQlEPkaNKv8f1FZYqwxtUPozn/fwXmTCr0pNJlNJyewgJZGF0g0kV6ukrDsHoy +EoJXduYm3yWwD4uPrnRBSpqxxXBubef0u6l3LxQl6uMHEHA4tcx0eAfyuFT9m+snhr/O/NaDv xkaJCEJ20d9jx0YBNb4kcqP3oj/1YPeXqZbQxCuUD/VxpkylVr/jUlza8L4NdKuB0UgnoQQ67A dGjQX/02C5TndMU8cgsbMs33awJwzyF7B175c/dK4xwfiB4cpsnnxPW4d6hlLQSVQWCW4iRsQw MfU= X-IronPort-AV: E=McAfee;i="6200,9189,9981"; a="17178836" X-IronPort-AV: E=Sophos;i="5.82,293,1613401200"; d="scan'208";a="17178836" Received: from unknown (HELO oym-r3.gw.nic.fujitsu.com) ([210.162.30.91]) by esa10.hc1455-7.c3s2.iphmx.com with ESMTP; 12 May 2021 18:27:44 +0900 Received: from oym-m3.gw.nic.fujitsu.com (oym-nat-oym-m3.gw.nic.fujitsu.com [192.168.87.60]) by oym-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 39EC91FB301 for ; Wed, 12 May 2021 18:27:44 +0900 (JST) Received: from m3051.s.css.fujitsu.com (m3051.s.css.fujitsu.com [10.134.21.209]) by oym-m3.gw.nic.fujitsu.com (Postfix) with ESMTP id 694B41533F for ; Wed, 12 May 2021 18:27:43 +0900 (JST) Received: from bionic.lxd (unknown [10.126.53.116]) by m3051.s.css.fujitsu.com (Postfix) with ESMTP id 482DD93; Wed, 12 May 2021 18:27:43 +0900 (JST) From: Naohiro Tamura To: libc-alpha@sourceware.org Subject: [PATCH v2 1/6] config: Added HAVE_AARCH64_SVE_ASM for aarch64 Date: Wed, 12 May 2021 09:26:40 +0000 Message-Id: <20210512092640.901076-1-naohirot@fujitsu.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210512092308.900998-1-naohirot@fujitsu.com> References: <20210512092308.900998-1-naohirot@fujitsu.com> X-TM-AS-GCONF: 00 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, SPF_HELO_PASS, SPF_NEUTRAL, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Naohiro Tamura Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" From: Naohiro Tamura This patch checks if assembler supports '-march=armv8.2-a+sve' to generate SVE code or not, and then define HAVE_AARCH64_SVE_ASM macro. --- config.h.in | 5 +++++ sysdeps/aarch64/configure | 28 ++++++++++++++++++++++++++++ sysdeps/aarch64/configure.ac | 15 +++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/config.h.in b/config.h.in index 99036b887f..13fba9bb8d 100644 --- a/config.h.in +++ b/config.h.in @@ -121,6 +121,11 @@ /* AArch64 PAC-RET code generation is enabled. */ #define HAVE_AARCH64_PAC_RET 0 +/* Assembler support ARMv8.2-A SVE. + This macro becomes obsolete when glibc increased the minimum + required version of GNU 'binutils' to 2.28 or later. */ +#define HAVE_AARCH64_SVE_ASM 0 + /* ARC big endian ABI */ #undef HAVE_ARC_BE diff --git a/sysdeps/aarch64/configure b/sysdeps/aarch64/configure index 83c3a23e44..4c1fac49f3 100644 --- a/sysdeps/aarch64/configure +++ b/sysdeps/aarch64/configure @@ -304,3 +304,31 @@ fi $as_echo "$libc_cv_aarch64_variant_pcs" >&6; } config_vars="$config_vars aarch64-variant-pcs = $libc_cv_aarch64_variant_pcs" + +# Check if asm support armv8.2-a+sve +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SVE support in assembler" >&5 +$as_echo_n "checking for SVE support in assembler... " >&6; } +if ${libc_cv_asm_sve+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat > conftest.s <<\EOF + ptrue p0.b +EOF +if { ac_try='${CC-cc} -c -march=armv8.2-a+sve conftest.s 1>&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + libc_cv_aarch64_sve_asm=yes +else + libc_cv_aarch64_sve_asm=no +fi +rm -f conftest* +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_sve" >&5 +$as_echo "$libc_cv_asm_sve" >&6; } +if test $libc_cv_aarch64_sve_asm = yes; then + $as_echo "#define HAVE_AARCH64_SVE_ASM 1" >>confdefs.h + +fi diff --git a/sysdeps/aarch64/configure.ac b/sysdeps/aarch64/configure.ac index 66f755078a..3347c13fa1 100644 --- a/sysdeps/aarch64/configure.ac +++ b/sysdeps/aarch64/configure.ac @@ -90,3 +90,18 @@ EOF fi rm -rf conftest.*]) LIBC_CONFIG_VAR([aarch64-variant-pcs], [$libc_cv_aarch64_variant_pcs]) + +# Check if asm support armv8.2-a+sve +AC_CACHE_CHECK(for SVE support in assembler, libc_cv_asm_sve, [dnl +cat > conftest.s <<\EOF + ptrue p0.b +EOF +if AC_TRY_COMMAND(${CC-cc} -c -march=armv8.2-a+sve conftest.s 1>&AS_MESSAGE_LOG_FD); then + libc_cv_aarch64_sve_asm=yes +else + libc_cv_aarch64_sve_asm=no +fi +rm -f conftest*]) +if test $libc_cv_aarch64_sve_asm = yes; then + AC_DEFINE(HAVE_AARCH64_SVE_ASM) +fi