| Message ID | 20210327183417.3390361-1-hjl.tools@gmail.com |
|---|---|
| State | Dropped |
| Headers |
Return-Path: <libc-alpha-bounces@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E60913857009; Sat, 27 Mar 2021 18:34:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E60913857009 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1616870081; bh=vpUvzGG/BSz0fqo05twPA4ysTTet2/NXGrGokXlxAcg=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=Jee+GYuCgS7PED4NszrT65fFvOYAL1obtA8Ujyec1Knb46P2kdDsGSowO7pzbQdL0 tzLoxk39oljNP3PttVkaQMa0/kGYLvsMxMCYBLYt83E8tSQO51m85Ycg1EuCGa6dei NtZg8/hrfNL6qDCc4NJMfdb9BN7Qhd2wa6dA9Nwo= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by sourceware.org (Postfix) with ESMTPS id 1245D385801A; Sat, 27 Mar 2021 18:34:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 1245D385801A Received: by mail-pg1-x529.google.com with SMTP id v3so6783521pgq.2; Sat, 27 Mar 2021 11:34:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vpUvzGG/BSz0fqo05twPA4ysTTet2/NXGrGokXlxAcg=; b=VHut8zKmWfRP77VmzZLTAWkF3+AAtesvN5PetDPRcsPQl9ikF1ESqQxsOKenUtddmc SZxmD6MOy+H6ozWE2iQNexBMZCwOKFPzm+nO8poFQ+NAU6l58XZn0MlIgrWICoN/mcj8 7sNXL5XZkj+sNtkEv8/xK1jJ/2qDoDRwNq9eGrzGj+uAc0q7Lk3vrVVb/YJviImTzEGl 5YoaHJbiI88cEfs1n18xsGdDCmaugrJEcDBvGSKZsZdC6+sUFTioc0YwdZjDwiMqNWtT lmy5/GG//sMV9/CA4o6sFN6SO/vK2XNYljxscMdp1s0N0y8vKv4jvBN6eYiJRheKBw1Y e/gA== X-Gm-Message-State: AOAM530Fy515NsAWjZh0ajls5ZZA1KcQ1uDgzv5L9o3k4G6WG+lS9IS6 u41GBMW+DnldyMfywiWXKNDNz6+yomsTCg== X-Google-Smtp-Source: ABdhPJyaHuNhaLw6s4a3fDl1vStF1tNIQVQ2km7Ee9mfPeQ4pLbcrtrP+MEO04JzmEAjAex3BMRSqQ== X-Received: by 2002:a05:6a00:1595:b029:217:49e9:2429 with SMTP id u21-20020a056a001595b029021749e92429mr17924057pfk.80.1616870076873; Sat, 27 Mar 2021 11:34:36 -0700 (PDT) Received: from gnu-cfl-2.localdomain ([172.56.38.37]) by smtp.gmail.com with ESMTPSA id x2sm4427772pfx.41.2021.03.27.11.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Mar 2021 11:34:36 -0700 (PDT) Received: from gnu-cfl-2.localdomain (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id C2B811A017F; Sat, 27 Mar 2021 11:34:34 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH] x86: Disable RTM on Skylake [BZ #27398] Date: Sat, 27 Mar 2021 11:34:17 -0700 Message-Id: <20210327183417.3390361-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3036.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> From: "H.J. Lu via Libc-alpha" <libc-alpha@sourceware.org> Reply-To: "H.J. Lu" <hjl.tools@gmail.com> Cc: Florian Weimer <fweimer@redhat.com>, Siddhesh Poyarekar <siddhesh@sourceware.org> Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces@sourceware.org> |
| Series |
x86: Disable RTM on Skylake [BZ #27398]
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Commit Message
H.J. Lu
March 27, 2021, 6:34 p.m. UTC
Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM feature. --- sysdeps/x86/cpu-features.c | 4 ++++ 1 file changed, 4 insertions(+)
Comments
* H. J. Lu via Libc-alpha: > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM > feature. > --- > sysdeps/x86/cpu-features.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > index d7248cbb45..3641a48407 100644 > --- a/sysdeps/x86/cpu-features.c > +++ b/sysdeps/x86/cpu-features.c > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) > with stepping >= 4) to avoid TSX on kernels that weren't > updated with the latest microcode package (which disables > broken feature by default). */ > + case 0x8e: > + case 0x9e: > + /* Disable RTM explicitly on Skylake since CPUID may report > + RTM feature incorrectly [BZ #27398]. */ > CPU_FEATURE_UNSET (cpu_features, RTM); > break; > } Won't this affect the server parts as well? I'm not sure if that's what our users want. We need to report the kernel bug properly, it got stalled because we initially suspected it might be a security bug.
On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote: > > * H. J. Lu via Libc-alpha: > > > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM > > feature. > > --- > > sysdeps/x86/cpu-features.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > index d7248cbb45..3641a48407 100644 > > --- a/sysdeps/x86/cpu-features.c > > +++ b/sysdeps/x86/cpu-features.c > > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) > > with stepping >= 4) to avoid TSX on kernels that weren't > > updated with the latest microcode package (which disables > > broken feature by default). */ > > + case 0x8e: > > + case 0x9e: > > + /* Disable RTM explicitly on Skylake since CPUID may report > > + RTM feature incorrectly [BZ #27398]. */ > > CPU_FEATURE_UNSET (cpu_features, RTM); > > break; > > } > > Won't this affect the server parts as well? I'm not sure if that's > what our users want. No since Xeon has a different model number (0x55). > We need to report the kernel bug properly, it got stalled because we > initially suspected it might be a security bug.
* H. J. Lu: > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote: >> >> * H. J. Lu via Libc-alpha: >> >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM >> > feature. >> > --- >> > sysdeps/x86/cpu-features.c | 4 ++++ >> > 1 file changed, 4 insertions(+) >> > >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c >> > index d7248cbb45..3641a48407 100644 >> > --- a/sysdeps/x86/cpu-features.c >> > +++ b/sysdeps/x86/cpu-features.c >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) >> > with stepping >= 4) to avoid TSX on kernels that weren't >> > updated with the latest microcode package (which disables >> > broken feature by default). */ >> > + case 0x8e: >> > + case 0x9e: >> > + /* Disable RTM explicitly on Skylake since CPUID may report >> > + RTM feature incorrectly [BZ #27398]. */ >> > CPU_FEATURE_UNSET (cpu_features, RTM); >> > break; >> > } >> >> Won't this affect the server parts as well? I'm not sure if that's >> what our users want. > > No since Xeon has a different model number (0x55). Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too.
On Sat, Mar 27, 2021 at 1:02 PM Florian Weimer <fw@deneb.enyo.de> wrote: > > * H. J. Lu: > > > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote: > >> > >> * H. J. Lu via Libc-alpha: > >> > >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM > >> > feature. > >> > --- > >> > sysdeps/x86/cpu-features.c | 4 ++++ > >> > 1 file changed, 4 insertions(+) > >> > > >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > >> > index d7248cbb45..3641a48407 100644 > >> > --- a/sysdeps/x86/cpu-features.c > >> > +++ b/sysdeps/x86/cpu-features.c > >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) > >> > with stepping >= 4) to avoid TSX on kernels that weren't > >> > updated with the latest microcode package (which disables > >> > broken feature by default). */ > >> > + case 0x8e: > >> > + case 0x9e: > >> > + /* Disable RTM explicitly on Skylake since CPUID may report > >> > + RTM feature incorrectly [BZ #27398]. */ > >> > CPU_FEATURE_UNSET (cpu_features, RTM); > >> > break; > >> > } > >> > >> Won't this affect the server parts as well? I'm not sure if that's > >> what our users want. > > > > No since Xeon has a different model number (0x55). > > Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too. Does it have RTM?
* H. J. Lu: >> Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too. > > Does it have RTM? Yes, it does. Maybe we should try to track down Siddhesh's bug instead?
On Sat, Mar 27, 2021 at 1:13 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > On Sat, Mar 27, 2021 at 1:02 PM Florian Weimer <fw@deneb.enyo.de> wrote: > > > > * H. J. Lu: > > > > > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote: > > >> > > >> * H. J. Lu via Libc-alpha: > > >> > > >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM > > >> > feature. > > >> > --- > > >> > sysdeps/x86/cpu-features.c | 4 ++++ > > >> > 1 file changed, 4 insertions(+) > > >> > > > >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c > > >> > index d7248cbb45..3641a48407 100644 > > >> > --- a/sysdeps/x86/cpu-features.c > > >> > +++ b/sysdeps/x86/cpu-features.c > > >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) > > >> > with stepping >= 4) to avoid TSX on kernels that weren't > > >> > updated with the latest microcode package (which disables > > >> > broken feature by default). */ > > >> > + case 0x8e: > > >> > + case 0x9e: > > >> > + /* Disable RTM explicitly on Skylake since CPUID may report > > >> > + RTM feature incorrectly [BZ #27398]. */ > > >> > CPU_FEATURE_UNSET (cpu_features, RTM); > > >> > break; > > >> > } > > >> > > >> Won't this affect the server parts as well? I'm not sure if that's > > >> what our users want. > > > > > > No since Xeon has a different model number (0x55). > > > > Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too. > > Does it have RTM? It does have TSX: https://ark.intel.com/content/www/us/en/ark/products/97469/intel-xeon-processor-e3-1240-v6-8m-cache-3-70-ghz.html Then my patch won't work.
On Sat, Mar 27, 2021 at 1:16 PM Florian Weimer <fw@deneb.enyo.de> wrote: > > * H. J. Lu: > > >> Hmm. Xeon E3-1240 v6 has model number 158 (0x9e), too. > > > > Does it have RTM? > > Yes, it does. > > Maybe we should try to track down Siddhesh's bug instead? Yes.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index d7248cbb45..3641a48407 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features) with stepping >= 4) to avoid TSX on kernels that weren't updated with the latest microcode package (which disables broken feature by default). */ + case 0x8e: + case 0x9e: + /* Disable RTM explicitly on Skylake since CPUID may report + RTM feature incorrectly [BZ #27398]. */ CPU_FEATURE_UNSET (cpu_features, RTM); break; }