From patchwork Tue Dec 29 11:47:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Huang Pei X-Patchwork-Id: 41580 X-Patchwork-Delegate: azanella@linux.vnet.ibm.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B76EF388A018; Tue, 29 Dec 2020 11:48:25 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 7B9023887016 for ; Tue, 29 Dec 2020 11:48:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7B9023887016 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=huangpei@loongson.cn Received: from localhost.localdomain (unknown [196.245.9.36]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dxj8thF+tfe0YHAA--.8248S3; Tue, 29 Dec 2020 19:48:14 +0800 (CST) From: Huang Pei To: Joseph Myers Subject: [PATCH V4 1/2] mips: add hp-timing support for MIPS R2 Date: Tue, 29 Dec 2020 19:47:40 +0800 Message-Id: <20201229114741.14685-2-huangpei@loongson.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201229114741.14685-1-huangpei@loongson.cn> References: <20201229114741.14685-1-huangpei@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Dxj8thF+tfe0YHAA--.8248S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr1ruF1xCF1fXF4rGFy3Jwb_yoW8Kw48pF 4kCF45GF4kX3y2k3WfXFsrGF15tFZ5Xr15KF13CrW3Jwn8JFyrXrW29ryYgw1xJFyxuF97 ZFW7WFyUuan7AFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBF14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1Y6r1xM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE47Wl42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUHHq7UUUUU= X-CM-SenderInfo: xkxd0whshlqz5rrqw2lrqou0/ X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Chenghua Xu , libc-alpha Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" MIPS R2 only support 32 bit TSC(AKA "rdhwr %0, $2"), but it should be enough for rtld. Linux/MIPS kernel added emulation for 'rdhwr %0, $2'，uncondionally. Userspace CAN NOT tell directly whether 'rdhwr' is not implemented, or disabled (by clear bit[2] of CP0 Hwena). If you had any doubt on the precision of 'rdhwr %0, $2', DO check both your hardware and software environment(such as in a para-virtualized guest). --- sysdeps/mips/hp-timing.h | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 sysdeps/mips/hp-timing.h diff --git a/sysdeps/mips/hp-timing.h b/sysdeps/mips/hp-timing.h new file mode 100644 index 0000000000..43cb695f2f --- /dev/null +++ b/sysdeps/mips/hp-timing.h @@ -0,0 +1,44 @@ +/* High precision, low overhead timing functions. MIPS version. + Copyright (C) 2020 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Huang Pei , 2020. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _HP_TIMING_MIPS_H +#define _HP_TIMING_MIPS_H 1 + +#if IS_IN(rtld) && __mips_isa_rev >= 2 +/* MIPS R2 always have the timestamp register. but it's got only 8 seconds + * range, assuming half of cpu frequence 800Mhz . Use it for ld.so + * profiling only*/ +#define HP_TIMING_INLINE (1) + +/* We use 32bit values for the times. */ +typedef unsigned int hp_timing_t; + +/* Read the cp0 count, this maybe inaccurate. */ +#define HP_TIMING_NOW(Var) \ + ({ unsigned int _count; \ + asm volatile ("rdhwr\t%0,$2" : "=r" (_count)); \ + (Var) = _count; }) + +# include + +#else +# include +#endif /* IS_IN(rtld) && __mips_isa_rev >= 2 */ + +#endif /* hp-timing.h */