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[69.181.90.243]) by smtp.gmail.com with ESMTPSA id 184sm4562397pgi.92.2020.12.21.20.22.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Dec 2020 20:22:03 -0800 (PST) Received: from gnu-cfl-2.localdomain (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 350071A00EA for ; Mon, 21 Dec 2020 20:22:02 -0800 (PST) To: libc-alpha@sourceware.org Subject: [PATCH] : Add Intel LAM support Date: Mon, 21 Dec 2020 20:22:00 -0800 Message-Id: <20201222042200.2808179-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-Spam-Status: No, score=-3040.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Add Intel Linear Address Masking (LAM) support to . --- manual/platform.texi | 3 +++ sysdeps/x86/sys/platform/x86.h | 3 +++ sysdeps/x86/tst-get-cpu-features.c | 1 + 3 files changed, 7 insertions(+) diff --git a/manual/platform.texi b/manual/platform.texi index 8fec2933d6..b67683aeb3 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -377,6 +377,9 @@ the indirect branch predictor barrier (IBPB). @item @code{KL} -- AES Key Locker instructions. +@item +@code{LAM} -- Linear Address Masking. + @item @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR. diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h index 3ef92b04e8..99d8c9b0ab 100644 --- a/sysdeps/x86/sys/platform/x86.h +++ b/sysdeps/x86/sys/platform/x86.h @@ -317,6 +317,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define bit_cpu_FSRS (1u << 11) #define bit_cpu_FSRCS (1u << 12) #define bit_cpu_HRESET (1u << 22) +#define bit_cpu_LAM (1u << 26) /* COMMON_CPUID_INDEX_19. */ @@ -541,6 +542,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define index_cpu_FSRS COMMON_CPUID_INDEX_7_ECX_1 #define index_cpu_FSRCS COMMON_CPUID_INDEX_7_ECX_1 #define index_cpu_HRESET COMMON_CPUID_INDEX_7_ECX_1 +#define index_cpu_LAM COMMON_CPUID_INDEX_7_ECX_1 /* COMMON_CPUID_INDEX_19. */ @@ -765,6 +767,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int) #define reg_FSRS eax #define reg_FSRCS eax #define reg_HRESET eax +#define reg_LAM eax /* COMMON_CPUID_INDEX_19. */ diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c index 667aa27117..6f1e925a6a 100644 --- a/sysdeps/x86/tst-get-cpu-features.c +++ b/sysdeps/x86/tst-get-cpu-features.c @@ -227,6 +227,7 @@ do_test (void) CHECK_CPU_FEATURE (FSRS); CHECK_CPU_FEATURE (FSRCS); CHECK_CPU_FEATURE (HRESET); + CHECK_CPU_FEATURE (LAM); CHECK_CPU_FEATURE (AESKLE); CHECK_CPU_FEATURE (WIDE_KL);