From patchwork Sat Jan 27 03:57:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 25596 Received: (qmail 104209 invoked by alias); 27 Jan 2018 03:58:05 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 104128 invoked by uid 89); 27 Jan 2018 03:58:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-spam-relays-external:209.85.160.68, H*RU:209.85.160.68, HX-Received:sk:3-v6mr1 X-HELO: mail-pl0-f68.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=siYxFOFadEubF0flDv9GZrZG80xzJyHXtOOM6cxgKD8=; b=iB84Gw0fPId0gsJgaigJ2nknz5dZCjtB6s/Ca7Q0uvqNfiyQrX4vg43IlwWgcPSIaG psB8Sbhh2Ms0QcM3WdvEw10W+woy80YPKo4xib16qOoLTmIxMPDDM5ZyiLfg5Kn+dJsb dyb9EmR6gETnBDTbpqGHoNrGXdQhKugopW8CI0AbCU844hfZ+V2HRGaW55+5sKcfap2l pT6mrqAkcWcYkoAh21pl8VQLO99oQ5e+yXWeLwKr1aDHdBjOkgb0QZaGkbDprrbYp+JT IytDM4AnpdNlQ+u7rVse7uRtzChVPo0j0ElHoZiYoJhpbHWbaz97GX6UiCe32bByH0Wq Aiww== X-Gm-Message-State: AKwxytdrHaG7lOYqSXCA2dYtRNow6ma7jP+L8JevNDDaxd2AoSTccQjG S79mHobhJdT5cb5KNB3ENzFbhA== X-Google-Smtp-Source: AH8x225HnZ9LVviNp6ZEiG7HO/iEvwkH0GPUaifKWuTGIas5Ts0jyc073B2lXJvzljCyuuI2wplWWQ== X-Received: by 2002:a17:902:203:: with SMTP id 3-v6mr16588509plc.413.1517025481814; Fri, 26 Jan 2018 19:58:01 -0800 (PST) Subject: [PATCH v7 04/17] Add documentation for __riscv_flush_icache Date: Fri, 26 Jan 2018 19:57:31 -0800 Message-Id: <20180127035744.10058-5-palmer@dabbelt.com> In-Reply-To: <20180127035744.10058-1-palmer@dabbelt.com> References: <20180127035744.10058-1-palmer@dabbelt.com> Cc: Palmer Dabbelt From: Palmer Dabbelt To: libc-alpha@sourceware.org, joseph@codesourcery.com This function is used by GCC to enforce ordering between data writes and instruction fetches, and while we'd prefer that users rely on the GCC intrinsic when possible this is user visible in case that's not possible. 2018-01-26 Palmer Dabbelt * manual/platform.texi: Add RISC-V documenation for __riscv_flush_icache. --- manual/platform.texi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/manual/platform.texi b/manual/platform.texi index cb166641fb71..b8721a071272 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -6,6 +6,7 @@ @menu * PowerPC:: Facilities Specific to the PowerPC Architecture +* RISC-V:: Facilities Specific to the RISC-V Architecture @end menu @node PowerPC @@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time interval expires or if an attempt is made to set the priority to medium high when it is not allowed, the priority is set to medium. @end deftypefun + +@node RISC-V +@appendixsec RISC-V-specific Facilities + +Cache management facilities specific to RISC-V systems that implement the Linux +ABI are declared in @file{sys/cachectl.h}. + +@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags}) +@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}} +Enforce ordering between stores and instruction cache fetches. The range of +addresses over which ordering is enforced is specified by @var{start} and +@var{end}. The @var{flags} argument controls the extent of this ordering, with +the default behavior (a @var{flags} value of 0) being to enforce the fence on +all threads in the current process. Setting the +@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing +ordering on only the current thread is necessary. All other flag bits are +reserved. +@end deftypefun