From patchwork Thu Jun 8 22:57:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 20873 X-Patchwork-Delegate: tuliom@linux.vnet.ibm.com Received: (qmail 107686 invoked by alias); 8 Jun 2017 22:57:38 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 107617 invoked by uid 89); 8 Jun 2017 22:57:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Benjamin, benjamin X-HELO: mail-qt0-f193.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wVODqu+Oi83adaHE/oA9gdi19ikBIWRZn9JqrhKxurU=; b=ZoOYFkJ0IExNXqim7Hsp7yJKPFpO0KKVyI6yTH1pTsU2IY81C/f4Mh4fVm3WB39pcY J77PMVps23v/mEmgYK0cG8/bZJiXwjl2MIx+6TPjEcW73G/yWRuJ9LyYwYqUELVrEwmx Tcz1mAUxz8WINEICpR/jJGowVNC3a8qnBugsYSvs9iFU48JxU6+KKXlMJIoeGZAasCrS t/H5gOab5I9c0Z5jxQemlu0X1cS+uMy66bFBY8+LyEYRZrJ9uAn9m/BVGumk5owfpzgu 78MaDbYWJ0X/W2Uv/0UkBn1eaDZ4P59xkj+H6+wLs8MQdpV3LBCtw+3jhSRcXX3Lh6kx yyaA== X-Gm-Message-State: AKS2vOwsiBU70R2pyBuwzV19WuHjGfOyEKTBpLVPXpFLfLVAyBWdOUlS wQ3JYIHIrYtlzCWogw8= X-Received: by 10.200.14.66 with SMTP id j2mr26368992qti.229.1496962657316; Thu, 08 Jun 2017 15:57:37 -0700 (PDT) From: Richard Henderson To: libc-alpha@sourceware.org Cc: Benjamin Herrenschmidt , Steven Munroe Subject: [PATCH 3/3] Add cache info for powerpc64 Date: Thu, 8 Jun 2017 15:57:28 -0700 Message-Id: <20170608225728.26779-4-rth@twiddle.net> In-Reply-To: <20170608225728.26779-1-rth@twiddle.net> References: <20170608225728.26779-1-rth@twiddle.net> The actual cache info was added for 4.11, but have a guess at the L1 linesizes using info provided by older kernels. * sysdeps/unix/sysv/linux/powerpc/powerpc64/sysconf.c: New file. Cc: Benjamin Herrenschmidt Cc: Steven Munroe --- .../unix/sysv/linux/powerpc/powerpc64/sysconf.c | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/powerpc/powerpc64/sysconf.c diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/sysconf.c b/sysdeps/unix/sysv/linux/powerpc/powerpc64/sysconf.c new file mode 100644 index 0000000..9cac9df --- /dev/null +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/sysconf.c @@ -0,0 +1,90 @@ +/* Copyright (C) 2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#include +#include +#include +#include +#include + + +static long int linux_sysconf (int name); + +/* Get the value of the system variable NAME. */ +long int +__sysconf (int name) +{ + unsigned long tmp; + + /* The auxv entries describing the proper cache geometry were + added for kernel 4.11. Thankfully, getauxval returns 0 when + the entry isn't present and is also the return from sysconf + when the value is unknown. + + For the L1 linesize names, when the proper auxv entries are + not present, we fall back on older auxv entries that provide + the "block" linesize used for cache flushing. It is a fair + guess that this does in fact correspond to the L1 shape. */ + switch (name) + { + case _SC_LEVEL1_ICACHE_SIZE: + return getauxval(AT_L1I_CACHESIZE); + case _SC_LEVEL1_ICACHE_ASSOC: + return (getauxval(AT_L1I_CACHEGEOMETRY) >> 16) & 0xffff; + case _SC_LEVEL1_ICACHE_LINESIZE: + tmp = getauxval(AT_L1I_CACHEGEOMETRY); + if (tmp) + return tmp & 0xffff; + return getauxval(AT_ICACHEBSIZE); + + case _SC_LEVEL1_DCACHE_SIZE: + return getauxval(AT_L1D_CACHESIZE); + case _SC_LEVEL1_DCACHE_ASSOC: + return (getauxval(AT_L1D_CACHEGEOMETRY) >> 16) & 0xffff; + case _SC_LEVEL1_DCACHE_LINESIZE: + tmp = getauxval(AT_L1D_CACHEGEOMETRY); + if (tmp) + return tmp & 0xffff; + return getauxval(AT_DCACHEBSIZE); + + case _SC_LEVEL2_CACHE_SIZE: + return getauxval(AT_L2_CACHESIZE); + case _SC_LEVEL2_CACHE_ASSOC: + return (getauxval(AT_L2_CACHEGEOMETRY) >> 16) & 0xffff; + case _SC_LEVEL2_CACHE_LINESIZE: + return getauxval(AT_L2_CACHEGEOMETRY) & 0xffff; + + case _SC_LEVEL3_CACHE_SIZE: + return getauxval(AT_L3_CACHESIZE); + case _SC_LEVEL3_CACHE_ASSOC: + return (getauxval(AT_L3_CACHEGEOMETRY) >> 16) & 0xffff; + case _SC_LEVEL3_CACHE_LINESIZE: + return getauxval(AT_L3_CACHEGEOMETRY) & 0xffff; + + case _SC_LEVEL4_CACHE_SIZE: + case _SC_LEVEL4_CACHE_ASSOC: + case _SC_LEVEL4_CACHE_LINESIZE: + return 0; + } + + return linux_sysconf (name); +} + +/* Now the generic Linux version. */ +#undef __sysconf +#define __sysconf static linux_sysconf +#include