diff mbox

Remove sparcv8 support

Message ID 17b6735b-7376-bb70-5b70-c53fa6fb2c87@mellanox.com
State New, archived
Headers

Commit Message

Chris Metcalf Nov. 10, 2016, 6:22 p.m. UTC 
  On 11/10/2016 12:08 PM, Torvald Riegel wrote:
> Looking at tile's atomic-machine.h files again, it seems we're not
> actually enforcing that atomic stores are atomic wrt. the CAS
> implementation in the kernel.
> The default implementation for atomic_store_relaxed in include/atomic.h
> does a plain memory store instead of falling back to exchange.  This is
> the right approach by default, I think, because that's what
> pre-C11-concurrency code in glibc does (ie, there's no abstraction for
> an atomic store at all, and plain memory accesses are used).
>
> However, if we emulate CAS with locks or such in the kernel, atomic
> stores need to synchronize with the CAS.  This would mean that all archs
> such as tile or sparc that do that have to define atomic_store_relaxed
> to fix this (at least for code converted to using C11 atomics, all
> nonconverted code might still do the wrong thing).

Note that our mainstream tilegx architecture has full atomic support, so
this is only applicable to the older tilepro architecture.

2016-11-10  Chris Metcalf  <cmetcalf@mellanox.com>

     * sysdeps/tile/tilepro/atomic-machine.h (atomic_store_relaxed)
     (atomic_store_acquire): Provide tilepro-specific implementations.

Comments

Torvald Riegel Nov. 10, 2016, 11:38 p.m. UTC | #1 
On Thu, 2016-11-10 at 13:22 -0500, Chris Metcalf wrote:
> On 11/10/2016 12:08 PM, Torvald Riegel wrote:
> > Looking at tile's atomic-machine.h files again, it seems we're not
> > actually enforcing that atomic stores are atomic wrt. the CAS
> > implementation in the kernel.
> > The default implementation for atomic_store_relaxed in include/atomic.h
> > does a plain memory store instead of falling back to exchange.  This is
> > the right approach by default, I think, because that's what
> > pre-C11-concurrency code in glibc does (ie, there's no abstraction for
> > an atomic store at all, and plain memory accesses are used).
> >
> > However, if we emulate CAS with locks or such in the kernel, atomic
> > stores need to synchronize with the CAS.  This would mean that all archs
> > such as tile or sparc that do that have to define atomic_store_relaxed
> > to fix this (at least for code converted to using C11 atomics, all
> > nonconverted code might still do the wrong thing).
> 
> Note that our mainstream tilegx architecture has full atomic support, so
> this is only applicable to the older tilepro architecture.

LGTM, thanks.
diff mbox

Patch

diff --git a/sysdeps/tile/tilepro/atomic-machine.h b/sysdeps/tile/tilepro/atomic-machine.h
index 702e17d77db7..5365929c940a 100644
--- a/sysdeps/tile/tilepro/atomic-machine.h
+++ b/sysdeps/tile/tilepro/atomic-machine.h
@@ -83,6 +83,16 @@  int __atomic_update_32 (volatile int *mem, int mask, int addend)
    ({ __typeof (mask) __att1_v = (mask);                 \
      __atomic_update ((mem), ~__att1_v, __att1_v); })

+/*
+ * We must use the kernel atomics for atomic_store, since otherwise an
+ * unsynchronized store could become visible after another core's
+ * kernel-atomic implementation had read the memory word in question,
+ * but before it had written the updated value to it, which would
+ * cause the unsynchronized store to be lost.
+ */
+#define atomic_store_relaxed(mem, val) atomic_exchange_acq (mem, val)
+#define atomic_store_release(mem, val) atomic_exchange_rel (mem, val)
+
  #include <sysdeps/tile/atomic-machine.h>

  #endif /* atomic-machine.h */