From patchwork Thu Sep 19 18:46:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 34600 Received: (qmail 72251 invoked by alias); 19 Sep 2019 18:47:12 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 72202 invoked by uid 89); 19 Sep 2019 18:47:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 5/6] [powerpc] __fesetround_inline optimizations Date: Thu, 19 Sep 2019 13:46:49 -0500 Message-Id: <1568918810-20393-6-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" On POWER9, use more efficient means to update the 2-bit rounding mode via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions or one 'mtfsfi' instruction that modifies 4 bits). Suggested-by: Paul E. Murphy 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use 'mffscrn' instruction on POWER9. (__fesetround_inline_nocheck): Likewise. Reviewed-By: Paul E Murphy --- v2: No change. sysdeps/powerpc/fpu/fenv_libc.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 53de1c8..3b91340 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -156,7 +156,12 @@ typedef union static inline int __fesetround_inline (int round) { - if ((unsigned int) round < 2) +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else if ((unsigned int) round < 2) { asm volatile ("mtfsb0 30"); if ((unsigned int) round == 0) @@ -172,7 +177,7 @@ __fesetround_inline (int round) else asm volatile ("mtfsb1 31"); } - +#endif return 0; } @@ -181,7 +186,14 @@ __fesetround_inline (int round) static inline void __fesetround_inline_nocheck (const int round) { - asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else + asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#endif } #define FPSCR_MASK(bit) (1 << (31 - (bit)))