From patchwork Thu Sep 19 18:46:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 34595 Received: (qmail 70124 invoked by alias); 19 Sep 2019 18:46:58 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70077 invoked by uid 89); 19 Sep 2019 18:46:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=HX-Languages-Length:2220 X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 2/6] [powerpc] No need to enter "Ignore Exceptions Mode" Date: Thu, 19 Sep 2019 13:46:46 -0500 Message-Id: <1568918810-20393-3-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" Since at least POWER8, there is no performance advantage to entering "Ignore Exceptions Mode", and doing so conditionally requires the conditional logic as well as a system call. Make it a no-op. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h: (__ENTER_NON_STOP): New. (__EXIT_NON_STOP): New. (__TEST_AND_ENTER_NON_STOP): Use __ENTER_NON_STOP. (__TEST_AND_EXIT_NON_STOP): Use __EXIT_NON_STOP. Reviewed-By: Paul E Murphy --- v2: This is a new patch in the series. sysdeps/powerpc/fpu/fenv_libc.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index bc2684e..549defa 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -27,6 +27,14 @@ extern const fenv_t *__fe_nomask_env_priv (void); extern const fenv_t *__fe_mask_env (void) attribute_hidden; +#ifdef _ARCH_PWR8 +/* There is no performance advantage to non-stop mode. */ +#define __ENTER_NON_STOP() do {} while (0) +#else +#define __ENTER_NON_STOP() do { (void) __fe_mask_env (); } while (0) +#endif +#define __EXIT_NON_STOP() do { (void) __fe_nomask_env_priv (); } while (0) + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not @@ -34,7 +42,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; #define __TEST_AND_ENTER_NON_STOP(old, new) \ do { \ if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \ - (void) __fe_mask_env (); \ + __ENTER_NON_STOP (); \ } while (0) /* If the old env has no enabled exceptions and the new env has any enabled @@ -44,7 +52,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; #define __TEST_AND_EXIT_NON_STOP(old, new) \ do { \ if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \ - (void) __fe_nomask_env_priv (); \ + __EXIT_NON_STOP (); \ } while (0) /* The sticky bits in the FPSCR indicating exceptions have occurred. */