From patchwork Tue Aug 20 21:19:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 34200 Received: (qmail 111713 invoked by alias); 20 Aug 2019 21:19:58 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 111651 invoked by uid 89); 20 Aug 2019 21:19:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH 4/4] [powerpc] fegetenv_status: simplify instruction generation Date: Tue, 20 Aug 2019 16:19:45 -0500 In-Reply-To: <1566335985-14601-1-git-send-email-pc@us.ibm.com> References: <1566335985-14601-1-git-send-email-pc@us.ibm.com> x-cbid: 19082021-0052-0000-0000-000003EC9376 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011625; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01249686; UDB=6.00659730; IPR=6.01031235; MB=3.00028250; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-20 21:19:51 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19082021-0053-0000-0000-00006226BB02 Message-Id: <1566335985-14601-5-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fegetenv_status() wants to use the lighter weight instruction 'mffsl' for reading the Floating-Point Status and Control Register (FPSCR). It currently will use it directly if compiled '-mcpu=power9', and will perform a runtime check (cpu_supports("arch_3_00")) otherwise. Nicely, it turns out that the 'mffsl' instruction will decode to 'mffs' on architectures older than "arch_3_00" because the additional bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset of 'mffsl'. So, just generate 'mffsl'. 2019-08-20 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status_ISA300): Delete. (fegetenv_status): Generate 'mffsl' unconditionally. --- sysdeps/powerpc/fpu/fenv_libc.h | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 8ba4832..186612b 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -37,7 +37,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Equivalent to fegetenv_register, but only returns bits for status, exception enables, and mode. */ -#define fegetenv_status_ISA300() \ +#define fegetenv_status() \ ({register double __fr; \ __asm__ __volatile__ ( \ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \ @@ -45,18 +45,6 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; __fr; \ }) -#ifdef _ARCH_PWR9 -# define fegetenv_status() fegetenv_status_ISA300() -#elif defined __BUILTIN_CPU_SUPPORTS__ -# define fegetenv_status() \ - (__glibc_likely (__builtin_cpu_supports ("arch_3_00")) \ - ? fegetenv_status_ISA300() \ - : fegetenv_register() \ - ) -#else -# define fegetenv_status() fegetenv_register () -#endif - /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */ #define fesetenv_register(env) \ do { \